Investigation of WO3/ZnO thin-film heterojunction-based Schottky diodes for H2 gas sensing

postprin

Improved performance of Pd/WO3/SiC Schottky-diode hydrogen gas sensor by using fluorine plasma treatment

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Improved Performances Of Metal-Oxide-Nitride-Oxide-Silicon Memory With Hftion as Charge Trapping Layer

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Passivation of Oxide Traps and Interface States in GaAs Metal-Oxide-Semiconductor Capacitor by LaTaON Passivation Layer and Fluorine Incorporation

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Interface-state-induced degradation of GIDL current in n-MOSFETsunder hot-carrier stress

The dependence of increase in post-stress gate-induced-drain-leakage (GIDL) current in n-MOSFET's on creation of interface states (ΔDit) during hot-carrier stress with VG = 0.5 VD was investigated. An interface-trap-assisted tunneling conduction mechanism is proposed to account for the increase. The stress method of VG = 0.5 VD can generate a lot of interface traps near the valence band in thermal oxide samples, which is considerably suppressed in nitrided oxide samples. From the linear relationship between increase in post-stress GIDL current and created interface-state density during hot-carrier stress, ΔDit values can be estimated.published_or_final_versio

Nitrided SrTiO 3 as charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of SrTiO 3 with and without nitrogen incorporation were investigated based on Al/ Al 2 O 3/SrTiO 3/SiO 2 /Si (MONOS) capacitors. A Ti-silicate interlayer at the SrTiO 3/SiO 2 interface was confirmed by x-ray photoelectron spectroscopy and transmission electron microscopy. Compared with the MONOS capacitor with SrTiO 3 as charge-trapping layer (CTL), the one with nitrided SrTiO 3 showed a larger memory window (8.4 V at ±10 V sweeping voltage), higher P/E speeds (1.8 V at 1 ms +8 V) and better retention properties (charge loss of 38% after 10 4s), due to the nitrided SrTiO 3 film exhibiting higher dielectric constant, higher deep-level traps induced by nitrogen incorporation, and suppressed formation of Ti silicate between the CTL and SiO 2 by nitrogen passivation. © 2011 American Institute of Physics.published_or_final_versio

Fabrication and electrical characterization of MONOS memory with novel high-κ gate stack

A novel high-κ gate stack structure with HfON/SiO 2 as dual tunneling layer (DTL), AIN as charge storage layer (CSL) and HfAIO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si 3N 4/SiO 2 as DTL, HfO 2 as CSL and Al 2O 3 as BL. Results show a large memory window of 3.55 V at PIE voltage of +8 V/-I5 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAIO/AIN/(HfON/SiO 2)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-κ HfON/SiO 2 DTL, high trapping efficiency of the high-κ AIN material and effective blocking role of the high-κ HfAIO BL. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-52

Low-operating-voltage polymer thin-film transistors based on poly(3-hexylthiophene) with hafnium oxide as the gate dielectric

The effects of hafnium oxide $(hbox{HfO}-{2})$ gate dielectric annealing treatment in oxygen $(hbox{O}-{2})$ and ammonia $(hbox{NH}-{3})$ ambient on the electrical performance of polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are investigated. The PTFTs with $hbox{HfO}-{2}$ gate dielectric and also octadecyltrichlorosilane surface modification, prepared by spin-coating process, exhibit good performance, such as a small threshold voltage of $-$0.5 V and an operating voltage as low as $-$4 V. Results indicate that the PTFT with $hbox{NH}-{3}$-annealed $hbox{HfO}-{2}$ shows higher carrier mobility, larger on/off current ratio, smaller subthreshold swing, and lower threshold voltage than the PTFT with $hbox{O}-{2}$-annealed $hbox{HfO}-{2}$. Capacitancevoltage analysis for metal-polymer-oxide-silicon structures indicates that the better electrical performance of the PTFT with $hbox{NH}-{3}$ -annealed $hbox{HfO}-{2}$ is attributed to improved dielectric/polymer interface and reduced series resistance in the transistor. © 2006 IEEE.published_or_final_versio

Influences of processing technique on electrical characteristics of TVS used in communication systems

An improved technique is proposed in fabricating a semiconductor surge protection device which is used in high-speed wideband information transmission systems. In order to increase the surge handling capability of the device, a double p-type diffusion is used. Specifically, in the diffusion step of gallium, SiO2 is used as a mask to obtain a very small base width and to avoid the reduction of carrier lifetime. It is found that this is a very useful way to reduce the on-state voltage drop and therefore the energy dissipation of the device.published_or_final_versio

Negative gate-bias instability of ZnO thin-film transistors studied by current–voltage and capacitance–voltage analyses

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