Twisted geometries: A geometric parametrisation of SU(2) phase space

A cornerstone of the loop quantum gravity program is the fact that the phase space of general relativity on a fixed graph can be described by a product of SU(2) cotangent bundles per edge. In this paper we show how to parametrize this phase space in terms of quantities describing the intrinsic and extrinsic geometry of the triangulation dual to the graph. These are defined by the assignment to each triangle of its area, the two unit normals as seen from the two polyhedra sharing it, and an additional angle related to the extrinsic curvature. These quantities do not define a Regge geometry, since they include extrinsic data, but a looser notion of discrete geometry which is twisted in the sense that it is locally well-defined, but the local patches lack a consistent gluing among each other. We give the Poisson brackets among the new variables, and exhibit a symplectomorphism which maps them into the Poisson brackets of loop gravity. The new parametrization has the advantage of a simple description of the gauge-invariant reduced phase space, which is given by a product of phase spaces associated to edges and vertices, and it also provides an abelianisation of the SU(2) connection. The results are relevant for the construction of coherent states, and as a byproduct, contribute to clarify the connection between loop gravity and its subset corresponding to Regge geometries.Comment: 28 pages. v2 and v3 minor change

Non-commutative integrable systems on bb-symplectic manifolds

In this paper we study non-commutative integrable systems on $b$-Poisson manifolds. One important source of examples (and motivation) of such systems comes from considering non-commutative systems on manifolds with boundary having the right asymptotics on the boundary. In this paper we describe this and other examples and we prove an action-angle theorem for non-commutative integrable systems on a $b$-symplectic manifold in a neighbourhood of a Liouville torus inside the critical set of the Poisson structure associated to the $b$-symplectic structure

Fabrication of (Silicon)-Germanium on insulator substrates by the Germanium condensation technique

Since the mid-20th century, the electronics industry has enjoyed a phenomenal growth and is now one of the largest industries. Based on the implementation and combination of semiconductor devices, tremendous efforts in material science have allowed continuous improvements and innovations. Nowadays, electronic devices are omnipresent in our everyday life and find applications in communication, entertainment, transportation, energy, medicine... Yet, this quest for high technology products is not over and compels to more scientific and technological breakthroughs.Silicon (Si) and its oxide have played and still play an important role in microelectronics. Due to the large availability of Si on earth and the advantageous properties of its associated oxide, they remained for long time the heart of most of semiconductor devices. However, over the years, more and more materials needed to be introduced in combination with Si to produce better, smaller and faster devices. With devices now approaching the nanoscale, electrical transport properties within silicon appear as a limiting factor and researchers evaluate other semiconductors as possible substitute. Germanium (Ge) is one of the material candidates since it offers faster electrical transport over Si (2 times higher electron mobility and 4 times hole mobility) and is extensively investigated for more than a decade.Although the introduction of Ge in standard high volume manufacturing requires the development of all the process modules needed to fabricate devices (gate stack engineering, doping, contact formation...), the production of high quality substrates remains one of the important issues. This thesis work focuses on the fabrication of germanium on insulator (GeOI) and silicon-germanium on insulator (SGOI) by the Ge condensation technique (also referred as Ge enrichment technique). By selectively oxidizing the Si atoms of a SiGe film deposited on a silicon on insulator (SOI) substrate, a thinner SiGe layer having a higher Ge atomic fraction or eventually a pure Ge layer is obtained on a insulating layer. In particular, this study aims at giving fundamental understanding of the different processes involved during condensation in order to understand the limitations of the technique and to provide optimized process conditions. The oxidation and diffusion phenomena during the condensation process has been studied and analytical and numeric models have been developed in order to understand the impact of the different process and layer parameters. It has been shown that during the condensation process, there is a competition between the accumulation of Ge at the oxidizing interface (induced by the selective oxidation) and the intermixing in the SiGe film sustained by the diffusion. In order to maintain selectivity and good uniformity of the condensed SGOI, slow oxidation kinetics and fast diffusion within the SiGe film is required. Such conditions can be achieved using high temperature dry oxidation in combination with intermittent high temperature annealings in inert ambient. The developed models have also proven to be useful in predicting the evolution of the Ge atomic fraction during the condensation process. As a result, good control of the process is achieved and oxidation conditions can be predicted upfront for any given starting structure.Moreover relaxation phenomena during the condensation processhas been studied. It has shown that due to the increase of Ge content, the misfit strain is increasing in the condensed SGOI film and relaxation becomes energetically favored. This relaxation is mediated by the nucleation of misfit dislocations and their associated misfit dislocations. These dislocations tend to grow slowly in film with Ge content less than 60% so that strain is accumulating at the beginning of the condensation process. On the other hand, in high Ge content SGOI film, the misfit dislocation glide speed is enhanced and larger relaxation of the strain is observed. In high Ge atomic fraction SGOI, a threading dislocation density in the order of 1E8/cm2 was measured. This study has also shown that the dissociation of these dislocations is energetically favored and results in the formation of stacking faults. In addition the large stress level in combination with the weak elastic properties of SiO2 result in the multiplication of misfit dislocations by double cross-slip mechanism more than homogeneous nucleation. As a result, nanometer sized steps are formed at the SiGe/BOX interface as well as on the surface and a typical cross hatch pattern is formed on the surface.Electrical performance of condensed SGOI substrate has been studied at the wafer scale as well as in devices. An increase of the hole mobility with the Ge atomic fraction in SGOI film has been observed. Excellent hole mobility of more than 400 cm2/V/s has been measured in a 27nm SGOI with 93% Ge atomic fraction which represents afactor of 4 improvement over start of the art SOI wafers with similar thickness and a factor of 2 improvement over start of the art strained SOI wafers. On the other hand, the electron mobility was shown to degrade for Ge content superior to 50%. In addition, the study showed that the defects created at the SiGe/BOX interface during the condensation process result in an increase of the interface trap density. Next, state of the art pMOSFET have been fabricated on condensed SGOI. Mobility enhancement over Si as well as standard epitaxial Ge on Si substrates was demonstrated. In addition, leakage currents have also been shown to be reduced by the use of SGOI substrates due to the presence of the BOX. Finally the short channel control was also improved in these thin condensed SGOI substrates.status: publishe

Modified gradient approach to inverse scattering for binary objects in stratified media

International audienceWe are concerned herein with inverse scattering problems in stratified media and aspect-limited data configurations. In such configurations, the sources and receivers of the probing waves are located in a medium different from the one which contains the object under test. This results in a lack of information which enhances the inherent ill-posedness of the inverse problem. To make the problem more tractable, we assume that the test object is homogeneous with known constitutive parameters so that the inverse problem consists of reconstructing its shape and location. This non-linear inverse problem is solved using the modified gradient method in which the a priori information is introduced as a binary constraint. A cooling parameter is introduced at the same time, which allows us to control the evolution of the iterative process. The effectiveness of this algorithm is studied for three different physical applications

Development and characterizations of fine pitch flip-chip interconnection using silver sintering

International audienceFlip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Development and characterizations of fine pitch flip-chip interconnection using silver sintering

Flip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Low-temperature silver sintering by colloidal approach

ISBN 978-1-7281-6293-5International audienceThe interest of silver nanostructures has surged in recent years as they are becoming promising materials in a growing number of applications. In particular, they have received intense attention for their use as lead-free die attach materials, photoactive devices engineering or more broadly electronic packaging. One of the challenges is the elaboration of conductive and printable patterns by Low-Temperature and Pressureless Sintering Techniques (LTPST) to achieve electric circuits on heat-sensitive substrates such as paper, plastic, polymeric substrates. Here, we present a facile method for synthesizing conductive patterns at low temperature based on the formation of self-assembled Ag nanocubes on Active Metal Brazing (AMB) substrates. The elaboration of 3-D arrays with nanogap of 2-3 nm between the cubic building units allows to get dense and compact packed nanoparticle solids which sinter at lower temperature than conventional commercial silver pastes. The impact of the capping agent and the size of the building units on the sintering properties were investigated and discussed