Fabrication of (Silicon)-Germanium on insulator substrates by the Germanium condensation technique

Abstract

Since the mid-20th century, the electronics industry has enjoyed a phenomenal growth and is now one of the largest industries. Based on the implementation and combination of semiconductor devices, tremendous efforts in material science have allowed continuous improvements and innovations. Nowadays, electronic devices are omnipresent in our everyday life and find applications in communication, entertainment, transportation, energy, medicine... Yet, this quest for high technology products is not over and compels to more scientific and technological breakthroughs.Silicon (Si) and its oxide have played and still play an important role in microelectronics. Due to the large availability of Si on earth and the advantageous properties of its associated oxide, they remained for long time the heart of most of semiconductor devices. However, over the years, more and more materials needed to be introduced in combination with Si to produce better, smaller and faster devices. With devices now approaching the nanoscale, electrical transport properties within silicon appear as a limiting factor and researchers evaluate other semiconductors as possible substitute. Germanium (Ge) is one of the material candidates since it offers faster electrical transport over Si (2 times higher electron mobility and 4 times hole mobility) and is extensively investigated for more than a decade.Although the introduction of Ge in standard high volume manufacturing requires the development of all the process modules needed to fabricate devices (gate stack engineering, doping, contact formation...), the production of high quality substrates remains one of the important issues. This thesis work focuses on the fabrication of germanium on insulator (GeOI) and silicon-germanium on insulator (SGOI) by the Ge condensation technique (also referred as Ge enrichment technique). By selectively oxidizing the Si atoms of a SiGe film deposited on a silicon on insulator (SOI) substrate, a thinner SiGe layer having a higher Ge atomic fraction or eventually a pure Ge layer is obtained on a insulating layer. In particular, this study aims at giving fundamental understanding of the different processes involved during condensation in order to understand the limitations of the technique and to provide optimized process conditions. The oxidation and diffusion phenomena during the condensation process has been studied and analytical and numeric models have been developed in order to understand the impact of the different process and layer parameters. It has been shown that during the condensation process, there is a competition between the accumulation of Ge at the oxidizing interface (induced by the selective oxidation) and the intermixing in the SiGe film sustained by the diffusion. In order to maintain selectivity and good uniformity of the condensed SGOI, slow oxidation kinetics and fast diffusion within the SiGe film is required. Such conditions can be achieved using high temperature dry oxidation in combination with intermittent high temperature annealings in inert ambient. The developed models have also proven to be useful in predicting the evolution of the Ge atomic fraction during the condensation process. As a result, good control of the process is achieved and oxidation conditions can be predicted upfront for any given starting structure.Moreover relaxation phenomena during the condensation processhas been studied. It has shown that due to the increase of Ge content, the misfit strain is increasing in the condensed SGOI film and relaxation becomes energetically favored. This relaxation is mediated by the nucleation of misfit dislocations and their associated misfit dislocations. These dislocations tend to grow slowly in film with Ge content less than 60% so that strain is accumulating at the beginning of the condensation process. On the other hand, in high Ge content SGOI film, the misfit dislocation glide speed is enhanced and larger relaxation of the strain is observed. In high Ge atomic fraction SGOI, a threading dislocation density in the order of 1E8/cm2 was measured. This study has also shown that the dissociation of these dislocations is energetically favored and results in the formation of stacking faults. In addition the large stress level in combination with the weak elastic properties of SiO2 result in the multiplication of misfit dislocations by double cross-slip mechanism more than homogeneous nucleation. As a result, nanometer sized steps are formed at the SiGe/BOX interface as well as on the surface and a typical cross hatch pattern is formed on the surface.Electrical performance of condensed SGOI substrate has been studied at the wafer scale as well as in devices. An increase of the hole mobility with the Ge atomic fraction in SGOI film has been observed. Excellent hole mobility of more than 400 cm2/V/s has been measured in a 27nm SGOI with 93% Ge atomic fraction which represents afactor of 4 improvement over start of the art SOI wafers with similar thickness and a factor of 2 improvement over start of the art strained SOI wafers. On the other hand, the electron mobility was shown to degrade for Ge content superior to 50%. In addition, the study showed that the defects created at the SiGe/BOX interface during the condensation process result in an increase of the interface trap density. Next, state of the art pMOSFET have been fabricated on condensed SGOI. Mobility enhancement over Si as well as standard epitaxial Ge on Si substrates was demonstrated. In addition, leakage currents have also been shown to be reduced by the use of SGOI substrates due to the presence of the BOX. Finally the short channel control was also improved in these thin condensed SGOI substrates.status: publishe