On the Thermal Activation of Negative Bias Temperature Instability

The temperature dependence of negative bias temperature instability (NBTI) is investigated on 2.0nm SiO2 devices from temperatures ranging from 300K down to 6K with a measurement window of ~12ms to 100s. Results indicate that classic NBTI degradation is observed down to ~200K and rarely observed at temperatures below 140K in the experimental window. Since experimental results show the charge trapping component contributing to NBTI is thermally activated, the results cannot be explained with the conventionally employed elastic tunneling theory. A new mechanism is observed at temperatures below 200K where device performance during stress conditions improves rather than degrades with time, which is opposite to the classical NBTI phenomenon

Experimental Characterization of NBTI Effect on pMOSFET and CMOS Inverter

Peer ReviewedPostprint (published version

Device layout dependence of PBTI in back-gated IGZO TFTs

The attractive electrical and processing properties of IGZO-based TFTs make these devices promising in various applications, but primarily in BEOL logic and DRAM cells [1,2]. IGZO has been shown to meet the performance requirements of many applications such as display and DRAM selectors [2]. However, the reliability of industry relevant gate-dielectric based IGZO devices has been only recently tackled [3,4]. In addition, the role of device layout and channel geometry (depending on the target application) has not been investigated. In this work we systematically study BTI degradation in 2 main families of back-gated IGZO transistors based on a 10nm thermally grown SiO2 as gate-dielectric, each one differing in S/D access geometry and/or channel width. In the first one, the S/D contacts have very large area with ~5000μm2 (M0 devices), while the second one is based on much smaller contact area of 135nm × device width W (M1 device) (Fig1, left). For each family, gate lengths Lg spanning 2 orders of magnitude (from ~200nm to ~30μm) are investigated to detect short channel effects. Vth0 is extracted at a fixed current level of 100pA×W/L for both architectures (Fig 1., middle). While M0 devices suffer from a decrease of Vth0 as a function of Lg, the Vth of M1 devices is very stable for all measured Lg. Please click Download on the upper right corner to see the full abstract

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.Comment: Accepted for publication in IEEE Transactions on Nanotechnolog

Device‐to‐Materials Pathway for Electron Traps Detection in Amorphous GeSe‐Based Selectors

The choice of the ideal material employed in selector devices is a tough task both from the theoretical and experimental side, especially due to the lack of a synergistic approach between techniques able to correlate specific material properties with device characteristics. Using a material-to-device multiscale technique, we propose a reliable protocol for an efficient characterization of the active traps in amorphous GeSe chalcogenide. The resulting trap maps trace back the specific features of materials responsible for the measured findings, and connect them to an atomistic description of the sample. Our metrological approach can be straightforwardly extended to other materials and devices, which is very beneficial for an efficient material-device co-design and the optimization of novel technologies

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Trigger-When-Charged: A technique for directly measuring RTN and BTI-induced threshold voltage fluctuation under use-Vdd

Low power circuits are important for many applications, such as IoT. Device variations and fluctuations are challenging their design. Random telegraph noise (RTN) is an important source of fluctuation. To verify a design by simulation, one needs assessing the impact of fluctuation in both driving current, ΔId, and threshold voltage, ΔVth. Many early works, however, only measured RTN-induced ΔId. ΔVth was not directly measured because of two difficulties: its average value is low and it is highly dynamic. Early works often estimated ΔVth from ΔId/gm(Vg=Vdd), where gm is trans-conductance, without giving its accuracy. The objective of this work is to develop a new Trigger-When-Charged (TWC) technique for directly measuring the RTN-induced ΔVth. By triggering the measurement only when a trap is charged, measurement accuracy is substantially improved. It is found that there is a poor correlation between ΔId/gm(Vg=Vdd) and the directly measured ΔVth(Vg=Vth). The former is twice of the latter on average. The origin for this difference is analyzed. For the first time, the TWC is applied to evaluate device-to-device variations of the directly measured RTN-induced ΔVth without selecting devices

Impact of Individual Charged Gate-Oxide Defects on the Entire I D -V G Characteristic of Nanoscaled FETs

Index Terms-Nanoscale, negative bias temperature instability (NBTI), pMOSFET, reliability, time-dependent variability