1,668 research outputs found
Characterization of electrical crosstalk in 4T-APS arrays using TCAD simulations
TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the crosstalk between pixels through the study of the electric field distribution. The image sensor consists on a linear array of five pinned photodiodes (PPD) with their transmission gates, floating diffusion and reset transistors. The effect of the variations of the thickness of the epitaxial layer has been addressed as well. In fact, the depth of the boundary of the epitaxial layer affects quantum efficiency (QE) so a correlation with crosstalk has been identified.Ministerio de Economía y Competitividad TEC2015-66878-C3-1RJunta de Andalucía TIC 2012-2338Office of Naval Research (USA) N00014141035
Matrix Methods for the Dynamic Range Optimization of Continuous-TimeGm-CFilters
This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential G m - C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear G m - C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra's series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum. The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of fc = 34MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. Additionally, the filter features 12dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using G m-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1MHz, with 70mV of amplitude. The filter combines very low noise (peak root spectral noise density below 56nV/√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude) properties. The filter has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85°C temperature variation and ±5% power supply deviation). The filter occupies 13mm2 and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.Ministerio de Ciencia y Tecnología TIC2003-0235
System-level optimization of baseband filters for communication applications
In this paper, a design approach for the high-level synthesis of programmable continuous-time baseband filters able to achieve optimum trade-off among dynamic range, distortion behavior, mismatch tolerance and power area consumptions is presented. The proposed approach relies on building programming circuit elements as arrays of switchable unit cells and defines the synthesis as a constrained optimization problem with both continuous and discrete variables, this last representing the number of enabled cells of the arrays at each configuration. The cost function under optimization is, then, defined as a weighted combination of performance indices which are estimated from macromodels of the circuit elements. The methodology has been implemented in MATLAB™ and C++, and covers all the classical approximation techniques for filters, most common circuit topologies (namely, ladder simulation and cascaded biquad realizations) and both transconductance-C (Gm-C) and active-RC implementation approaches. The proposed synthesis strategy is illustrated with a programmable equal-ripple ladder Gm-C filter for a multi-band power-line communication modem.P.R.O.F.I.T. FIT-070000-2001-84
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band to counteract high frequency components attenuation. The filter shows a nominal cutoff frequency of fc=34 MHz , less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. The filter also exhibits low noise feature (peak root spectral noise density below 56nV√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude). It has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85° C temperature variation and ± 5% power supply deviation). Simulations show a typical power consumption of 450 mW @ 1.8V supply.Ministerio de Ciencia y Tecnología TIC2003-0235
Anotaciones sobre la vegetación nitrófila del Archipiélago de Columbretes (Castellón)
Notes on the nitrophilous plata communities of the Columbretes Archipelago (Castellón, eastern Spain)Palabras clave. Vegetación nitrófila, nomenclatura, lberoleyantina, España.Key words. Nitrophilous plant communities, nomenclature, Iberoleyantine, Spain
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation
Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to the best of our knowledge, this is first model to incorporate a trap-assisted tunneling mechanism, a cross-section temperature dependence of the traps, and the self-heating effect. Comparison with experimental data establishes the validity of the model.Junta de Andalucía TIC 2012-2338Ministerio de Economía y Competitividad TEC2015-66878-C3-1-ROffice of Naval Research (USA) N00014141035
Real-time phase correlation based integrated system for seizure detection
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.Ministerio de Economía y Competitividad TEC2016- 80923-
Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel versus conventional ones made with single p/n junctions. We propose a method to characterize and compare photodiodes sensitivity. For this purpose, a dedicated chip in the standard AMS 180-nm HV technology has been fabricated. Four different sensor structures were implemented and compared. Experimental results are provided. Measurements show sensitivity enhancement ranging from 55% to 70% within the 500-1100 nm spectral region. The larger increment is happening in the near infrared band (up to 62%). Such results make stacked photodiodes suitable candidates for the implementation of photosensors in vision chips designed for standard CMOS technologies.Ministerio de Economía y Competitividad TEC2012-33634, TEC2015-66878- C3-1-RJunta de Andalucía TIC 2012-2338Office of Naval Research (USA) N00014141035
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