Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest

MEC bajo TIN2013-42253-PThis paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for floating-point adders, multipliers, and converters. Experimental analysis demonstrates that HUB formats and the corresponding arithmetic units maintain the same accuracy as conventional ones. On the other hand, the implementation of these units, based on basic architectures, shows that HUB formats simultaneously improve area, speed, and power consumption. Specifically, based on data obtained from the synthesis, a HUB single-precision adder is about 14% faster but consumes 38% less area and 26% less power than the conventional adder. Similarly, a HUB single-precision multiplier is 17% faster, uses 22% less area, and consumes slightly less power than conventional multiplier. At the same speed, the adder and multiplier achieve area and power reductions of up to 50% and 40%, respectively

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems

The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on classical floating-point number systems, the implementation of those circuits can be highly improved. For a 16-bit numbers, by using the proposed format, the area and power consumption of a floating-point adder is reduced up to 70% whereas those parameters are maintained for the case of a multiplier.This work was supported in part by the Ministry of Education and Science of Spain and Junta of Andalucía under contracts TIN2013-42253-P and TIC-1692, respectively, and Universidad de Málaga.Campus de Excelencia Internacional Andalucía Tech

Normalizing or not normalizing? An open question for floating-point arithmetic in embedded systems

Emerging embedded applications lack of a specific standard when they require floating-point arithmetic. In this situation they use the IEEE-754 standard or ad hoc variations of it. However, this standard was not designed for this purpose. This paper aims to open a debate to define a new extension of the standard to cover embedded applications. In this work, we only focus on the impact of not performing normalization. We show how eliminating the condition of normalized numbers, implementation costs can be dramatically reduced, at the expense of a moderate loss of accuracy. Several architectures to implement addition and multiplication for non-normalized numbers are proposed and analyzed. We show that a combined architecture (adder-multiplier) can halve the area and power consumption of its counterpart IEEE-754 architecture. This saving comes at the cost of reducing an average of about 10 dBs the Signal-to-Noise Ratio for the tested algorithms. We think these results should encourage researchers to perform further investigation in this issue.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest

QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number representation system. This new representation allows performing round-tonearest at the same cost of truncation. Consequently, the rounding errors of the results are halved, which allows it to reduce the word-length by one bit. This reduction positively impacts on the area, delay and power consumption of the design.Ministry of Education and Science of Spain and Junta of Andalucía under contracts TIN2013-42253-P and TIC-1692, respectively, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Project based learning on industrial informatics: applying IoT to urban garden

Copyright (c) 2018 IEEEThe fast evolution of technologies forces teachers to trade content off for self-learning. PBL is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, we present our experience introducing project-based learning in the last year subject. New Internet of Things (IoT) topic allows us to carry out complete projects, integrating different technologies and tools. Moreover, the selection of open-source and standard free technologies makes easy and cheap the access to hardware and software platforms used. We carefully have picked communication, data management, and programming tools that we think would be attractive to our students. They can start making fast prototyping with little initial skills and, at the same time, these are serious and popular tools widely used in the industry. In this paper, we report on the design of a project-based learning for our course and the impact this has on the student satisfaction and motivation. Surveys taught us that tuning the courses towards developing real projects on the field, has a large impact on acceptance, learning objectives achievements and motivation towards the course content.”I Plan Propio Integral de Docencia de la Universidad de Málaga” y Proyecto de Innovación Educativa PIE17/085, de la Universidad de Málaga. Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

New formats for computing with real-numbers under round-to-nearest

An edited version of this work was accepted in IEEE Transactions on computers, DOI 10.1109/TC.2015.2479623In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional radix-R number systems. This technique allows performing radix complement and round to nearest without carry propagation with negligible time and hardware cost. Furthermore, the proposed formats have the same storage cost and precision as standard ones. Since conversion to conventional formats simply require appending one extra-digit to the operands, standard circuits may be used to perform arithmetic operations with operands under the new format. We also extend the features of the RN-representation system and carry out a thorough comparison between both representation systems. We conclude that the proposed representation system is generally more adequate to implement systems for computation with real number under round-to-nearest.Ministry of Education and Science of Spain under contracts TIN2013-42253-P

Floating Point Square Root under HUB Format

Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is required because it is performed simply by truncation. From a hardware point of view, the circuits implementing this representation save both area and time since rounding does not involve any carry propagation. Designs to perform the four basic operations have been proposed under HUB format recently. Nevertheless, the square root operation has not been confronted yet. In this paper we present an architecture to carry out the square root operation under HUB format for floating point numbers. The results of this work keep supporting the fact that the HUB representation involves simpler hardware than its conventional counterpart for computers requiring round-to-nearest mode.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tec

High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.

Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is extensively used in many machine learning algorithms, especially for pattern recognition and classification. U nfortunately, i t h as a q uadratic complexity, which results in very high computational costs. Furthermore, its data dependency made it also very difficult t o parallelize. Special attention has been paid to computing DTW on the edge, as a way to reduce the load of communication on Internet-of- Thing applications. In this work, we propose a minimum area implementation of the DTW algorithm in AMD FPGAs with optimal use of the resources. That is achieved by maximizing the use time of the resources and taking advantage of the inner structure of the AMD FPGAs. This architecture could be used in small devices or as a base for a multi-core implementation with very high-throughput.MCIN/AEI/10.13039/501100011033and European Union Next Generation EU/PRTR under Project TED2021- 131527B-I00; by the Fondo Europeo de Desarrollo Regional (UMA20-FEDERJA-059); and by AMD™(Xilinx™) University Program Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Fast HUB Floating-point Adder for FPGA

Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point adder for FPGA which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA.TIN2016- 80920-R, JA2012 P12-TIC-1692, JA2012 P12-TIC-147

Rehabitar el mercado Pere San : nuevo formato de mercado y revitalización del entorno urbano : Sant Cugat del Vallès, Barcelona

La plaza de Sant Pere junto con el mercado Pere San han tenido históricamente una condición de centralidad en el núcleo de Sant Cugat del Vallès. Pese a esto, las sucesivas extensiones del municipio y la pacificación del eje Monasterio-Estación han desplazado la actividad comercial del entorno del mercado. Es por esto que se propone una nueva manera de usar el edificio del mercado, concibiendo una habitabilidad distinta, descubriendo y potenciando sus cualidades intrínsecas. Mediante esto, se propone rehabitar el mercado usándolo como núcleo comercial, determinándolo como mercado de abastos, autoservicio, degustación y restauración en un único punto, preservando al máximo el edificio y plaza preexistentes. De este modo, mediante este nuevo formato de mercado, se consigue el objetivo de revitalizar el entorno urbano, entendiéndolo del mejor modo dentro de las circunstancias y preexistencias actuales