Oversampled analog-to-digital converter architectures based on pulse frequency modulation

Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs). Time-encoding based ADCs have become of great interest to the designer community due to the possibility of implementing mostly digital circuits, which are well suited for current deep-submicron CMOS processes. Within this topic, VCO-based ADCs are one of the most promising candidates. VCO-based ADCs have typically been analyzed considering the output phase of the oscillator as a state variable, similar to the state variables considered in __ modulation loops. Although this assumption might take us to functional designs (as verified by literature), it does not take into account neither the oscillation parameters of the VCO nor the deterministic nature of quantization noise. To overcome this issue, we propose an interpretation of these type of systems based on the pulse frequency modulation (PFM) theory. This permits us to analytically calculate the quantization noise, in terms of the working parameters of the system. We also propose a linear model that applies to VCO-based systems. Thanks to it, we can determine the different error processes involved in the digitization of the input data, and the performance limitations which these processes direct to. A generic model for any order open-loop VCO-based ADCs is made based on the PFM theory. However, we will see that only the first-order case and a second order approximation can be implemented in practice. The PFM theory also allows us to propose novel approaches to both single-stage and multistage VCObased architectures. We describe open-loop architectures such as VCO-based architectures with digital precoding, PFM-based architectures that can be used as efficient ADCs or MASH architectures with optimal noise-transfer-function (NTF) zeros. We also make a first approach to the proposal and analysis of closed loop architectures. At the same time, we deal with one of the main limitations of VCOs (especially those built with ring oscillators), which is the non-linear voltage to- frequency relation. In this document, we describe two techniques mitigate this phenomenon. Firstly, we propose to use a pulse width modulator in front of the VCO. This way, there are only two possible oscillation states. Consequently, the oscillator works linearly. To validate the proposed technique, an experimental prototype was implemented in a 40-nm CMOS process. The chip showed noise problems that degraded the expected resolution, but allowed us to verify that the potential performance was close to the expected one. A potential signal-to-noise-distortion ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming 2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar power consumption and linearity properties. Secondly, we used a pulse frequency modulator to implement a second ADC. The proposed architecture is intrinsically linear and uses a digital delay line to increase the resolution of the converter. One experimental prototype was implemented in a 40-nm CMOS process using one of these architectures. Proper results were measured from this prototype. These results allowed us to verify that the PFM-based architecture could be used as an efficient ADC. The measured peak SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an occupied area equal to 0.08 mm2. The architecture shows a great linearity, and in comparison to related work, it consumes less power and occupies similar area. In general, the theoretical analyses and the architectures proposed in the document are not restricted to any application. Nevertheless, in the case of the experimental chips, the specifications required for these converters were linked to communication applications (e.g. VDSL, VDSL2, or even G.fast), which means medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva para el diseño de convertidores analógico-digitales basados en osciladores controlados por tensión. Los convertidores analógico-digitales con codificación temporal han llamado la atención durante los últimos años de la comunidad de diseñadores debido a la posibilidad de implementarlos en su gran mayoría con circuitos digitales, los cuales son muy apropiados para los procesos de diseño manométricos. En este ámbito, los convertidores analógico-digitales basados en osciladores controlados por tensión son uno de los candidatos más prometedores. Los convertidores analógico-digitales basados en osciladores controlados por tensión han sido típicamente analizados considerando que la fase del oscilador es una variable de estado similar a las que se observan en los moduladores __. Aunque esta consideración puede llevarnos a diseños funcionales (como se puede apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de la modulación por frecuencia de pulsos. Esto nos permite calcular de forma analítica las ecuaciones que modelan el ruido de cuantificación en función de los parámetros de oscilación. Se propone también un modelo lineal para el análisis de convertidores analógico-digitales basados en osciladores controlados por tensión. Este modelo permite determinar las diferentes fuentes de error que se producen durante el proceso de digitalización de los datos de entrada y las limitaciones que suponen. Un modelo genérico de convertidor de cualquier orden se propone con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una aproximación al caso de segundo orden se pueden implementar en la práctica. La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas para la propuesta y el análisis tanto de arquitecturas de una sola etapa como de arquitecturas de varias etapas construidas con osciladores controlados por tensión. Se proponen y se describen arquitecturas en lazo abierto como son las basadas en osciladores controlador por tensión con moduladores digitales en la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como convertidores analógico-digitales eficientes o arquitecturas en cascada en las que se optimizan la distribución de los ceros en la función de transferencia del ruido. También se realiza una aproximación a la propuesta y el análisis de arquitecturas en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes de los osciladores controlados por tensión (especialmente en aquellos implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos técnicas cuyo objetivo es mitigar esta limitación. La primera técnica de corrección se basa en el uso de un modulador por ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y no se genera distorsión en los datos de salida. La técnica se propone de forma teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo la validación de la propuesta teórica se fabricó un prototipo experimental en un proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo que se mantiene el consumo así como la linealidad. A continuación, se propone la implementación de un convertidor analógico digital mediante un modulador por frecuencia de pulsos. La arquitectura propuesta es intrínsecamente lineal y hace uso de una línea de retraso digital con el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental, se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura, de la que se obtuvieron resultados notables. Estos resultados permitieron verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor analógico-digital eficiente. La arquitectura consigue una relación real señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en comparación con arquitecturas equivalentes, el consumo es menor mientras que el área ocupada se mantiene similar. En general, las aportaciones propuestas en este documento se pueden aplicar a cualquier tipo de aplicación, independientemente de los requisitos de resolución, ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones (VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media (9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman

Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation

Oversampled ADCs based on voltage-controlled oscillators have been analyzed using statistical models inherited from sigma-delta modulation. This letter shows that the discrete Fourier transform of a VCO-ADC output sequence can be calculated analytically for single tone inputs. The calculation is based on the transformation of the VCO output into a pulse frequency modulated signal that can be represented by a trigonometric series. Knowledge of the VCO-ADC output spectrum allows accurate evaluation of the SNDR dependence with the VCO oscillation frequency and gain constant. The SNDR predictions of the proposed model have been compared to behavioral simulations displaying only a deviation of 0.7 dBThis work was supported by the CICYT project under Grant TEC2010-16330.Publicad

Oversampled ADC based on pulse frequency modulator and TDC

Oversaw led converters based on voltage controlled ring oscillators are an attractive solution because of their digital implementation and simplicity. However, the voltage-to-frequency conversion of ring oscillators displays a poor linearity. Replacing the ring oscillator by a pulse frequency modulator (PFM) that provides improved linearity at the expense of feedback and analogue amplification is proposed. Compared to the equivalent continuous time sigma delta modulators, the PFM may be more tolerant to circuit impairments. In addition, the output data of the proposed architecture is a multibit sequence through the use of a time-to-digital converter TDC instead of a Flash quantiser or a multibit digital-to-analogue converter. A high dynamic range can be achieved without severe constraints on analogue mismatch or clock jitter

Towards ultra-low power consumption VAD architectures with mixed signal circuits

Proceedings of: 56th Edition IEEE ISCAS 2023 - IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, CA, USA.A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.This paper was supported by program H2020-MSCA-ITN-2020 grant Nr.956601

Aceleración hardware con FPGA de algoritmo para estegoanálisis

En este Proyecto se plantea el desarrollo de un sistema de estegoanálisis sobre hardware para imágenes en formato JPEG con el objetivo de ser implementado sobre una FPGA y conseguir tiempos de ejecución menores que el mismo sistema desarrollado sobre software. Se pretende conseguir la llamada aceleración hardware, aprovechando la capacidad de una FPGA para realizar operaciones simultáneas y ejecutar procesos concurrentes para conseguir reducciones de tiempo muy significativas que, al final, acaban significando un mayor número de imágenes analizadas por unidad de tiempo. El sistema ha sido desarrollado utilizando el lenguaje de diseño hardware VHDL, quedando conformado como un conjunto de módulos, sincronizados entre sí, que implementan cada una de las etapas necesarias para el análisis de una imagen, según el algoritmo de estegoanálisis usado. En este Proyecto el sistema no se llega finalmente a implementar sobre una FPGA, sino que su utilización se queda a nivel de simulación. A pesar de ello, sí que se ha llegado a sintetizar y mapear sobre una FPGA para comprobar la posibilidad de usar el sistema en la práctica. _______________________________________________________________________________________________This Project proposes the development of a JPEG steganalysis system on an FPGA. The objective of this system is getting smaller runtimes than the same system developed on software. Hardware acceleration is the main goal. The capacity of an FPGA is used for doing simultaneous actions and running concurrent processes in order to achieve very important time reductions. This means a greater number of images analyzed per time unit. The system has been developed using the VHDL hardware design language, being formed as a set of modules, synchronized with each other. It implements each of the necessary steps for the analysis of an image, according to the used steganalysis algorithm. In this Project, the system has not been finally prototyped in an FPGA. Simulations have been used for testing it. However, its design has been synthesized and mapped on an FPGA to verify the possibility of using the system in practice.Ingeniería Industria

VCO-based sturdy MASH ADC architecture

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations.This work was supported by the CICYT project TEC2014-56879-R, Spain

High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion

The aim of this conference is to offer the possibility to present and discuss new research results on the area of integrated circuits and systems and all its fields of application. A major emphasis has been given in the technical program to emerging topics such as electronic systems for artificial intelligence, reliability of circuits and devices, unconventional computing, smart sensors and other relevant topics. The conference on Design of Circuits and Integrated Systems (DCIS) is an international meeting for researchers in the highly active fields of micro- and nano-electronic circuits and integrated systems. It provides an excellent forum to present and discuss works on the emerging challenges offered by technology, in the areas of modeling, design, implementation and test of devices, circuits and systems. The 35th edition will be organized by Universidad Politécnica de Madrid

Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection

Proceeding of: 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), 20-22 November 2019, Bilbao, SpainThis work describes a simple way to improve the resolution of low-pass voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs) implemented with ring-oscillators. We propose to insert a passive resistive network into the differential delay cells of the oscillator to get additional interpolated phases. These interpolated phases are then injected to other similar oscillators. By increasing the number of phases coming from all the oscillators, the effective gain of the system is higher and enhances the resolution of the converter. To validate the idea, a prototype of an open-loop VCO-based ADC was built in VerilogA language with ring-oscillators designed with a 65-nm CMOS process. The results of transient simulations were compared to the results of a behavioral ideal model of the system built in MATLAB. As expected, the signal-to-noise ratio (SNR) was improved in concordance with the increase in the number of phases. Finally, it was checked that the proposed circuit used to extract and inject the interpolated phases did not penalize the total power consumption. The proposed circuit structure is particularly suitable for high-bandwidth applications, where the oversampling ratio (OSR) is strongly restricted and the gain is limited because of the oscillator non-linearity. Due to the highly digital nature of the VCO-based ADC structures, this solution may be of special interest to be implemented in new deep-submicron CMOS processes.This work was supported by the CICYT project TEC2017-82653-R, Spain.Publicad

VCO-based ADC with a simplified DAC for non-linearity correction

The performance of open-loop ADCs implemented with VCOs is limited by VCO non-linearity and first-order noise shaping. The resolution limitation imposed by first-order noise shaping can be compensated by a ring oscillator VCO with many output phases. Linearity can also be improved by using a feedback loop around the VCO closed with a DAC. However, a long ring oscillator may require a DAC with a prohibitive number of bits if feedback is used to compensate distortion. This Letter proposes an ADC architecture based on the Leslie-Singh Sigma-Delta (Σ∆) modulator that allows to implement a distortion correction loop around a VCO with a simplified DAC of few levels, yet keeping a large number of output quantisation levels to maintain resolution. The Letter discusses the system-level architecture and shows an implementation circuit example to verify the effective correction of distortion.This work has been supported by the CICYT project TEC2014-56879-R, Spain

Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs

Proceeding of: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS): August 9-12, 2020, Springfield, MA, USA: on-line proceedings.A new phase-encoded MAC cell is proposed for low power smart sensing applications. If digitization of the raw data is made through voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs), we may take the unsampled frequency-encoded output signal and connect it to the first layer of a neural network. Then that layer could be implemented with phase-encoded MAC accelerators, leading to an energy-efficient solution. The MAC cell does not only make the accumulation/subtraction and multiplication operation, but also the non-linear function which supposes a great advantage with respect to other equivalent cells. A circuit example is proposed in a 65-nm CMOS process and transient simulations prove the feasibility of the approach.Publicad