Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 7 64 pixels with 50 \ub5m 7 50 \ub5m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 \ub5m 7 50 \ub5m and single readout electrode 25 \ub5m 7 100 \ub5m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology

Design of analog front-ends for the RD53 demonstrator chip

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment

Trapping in irradiated p-on-n silicon sensors at fluences anticipated at the HL-LHC outer tracker

The degradation of signal in silicon sensors is studied under conditions expected at the CERN High-Luminosity LHC. 200 $\mu$m thick n-type silicon sensors are irradiated with protons of different energies to fluences of up to $3 \cdot 10^{15}$ neq/cm$^2$. Pulsed red laser light with a wavelength of 672 nm is used to generate electron-hole pairs in the sensors. The induced signals are used to determine the charge collection efficiencies separately for electrons and holes drifting through the sensor. The effective trapping rates are extracted by comparing the results to simulation. The electric field is simulated using Synopsys device simulation assuming two effective defects. The generation and drift of charge carriers are simulated in an independent simulation based on PixelAV. The effective trapping rates are determined from the measured charge collection efficiencies and the simulated and measured time-resolved current pulses are compared. The effective trapping rates determined for both electrons and holes are about 50% smaller than those obtained using standard extrapolations of studies at low fluences and suggests an improved tracker performance over initial expectations

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Pixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project

Characterisation of irradiated thin silicon sensors for the CMS phase II pixel upgrade

The high luminosity upgrade of the Large Hadron Collider, foreseen for 2026, necessitates the replacement of the CMS experiment's silicon tracker. The innermost layer of the new pixel detector will be exposed to severe radiation, corresponding to a 1 MeV neutron equivalent fluence of up to Phi(eq) = 2x10(16) cm(-2), and an ionising dose of approximate to 5 MGy after an integrated luminosity of 3000 fb(-1). Thin, planar silicon sensors are good candidates for this application, since the degradation of the signal produced by traversing particles is less severe than for thicker devices. In this paper, the results obtained from the characterisation of 100 and 200 mu m thick p-bulk pad diodes and strip sensors irradiated up to fluences of Phi(eq) = 1.3 x 10(16) cm(-2) are shown.Peer reviewe

Selection of the silicon sensor thickness for the Phase-2 upgrade of the CMS Outer Tracker

During the operation of the CMS experiment at the High-Luminosity LHC the silicon sensors of the Phase-2 Outer Tracker will be exposed to radiation levels that could potentially deteriorate their performance. Previous studies had determined that planar float zone silicon with n-doped strips on a p-doped substrate was preferred over p-doped strips on an n-doped substrate. The last step in evaluating the optimal design for the mass production of about 200 m$^{2}$ of silicon sensors was to compare sensors of baseline thickness (about 300 μm) to thinned sensors (about 240 μm), which promised several benefits at high radiation levels because of the higher electric fields at the same bias voltage. This study provides a direct comparison of these two thicknesses in terms of sensor characteristics as well as charge collection and hit efficiency for fluences up to 1.5 × 10$^{15}$ n$_{eq}$/cm$^{2}$. The measurement results demonstrate that sensors with about 300 μm thickness will ensure excellent tracking performance even at the highest considered fluence levels expected for the Phase-2 Outer Tracker

Test beam performance of a CBC3-based mini-module for the Phase-2 CMS Outer Tracker before and after neutron irradiation

The Large Hadron Collider (LHC) at CERN will undergo major upgrades to increase the instantaneous luminosity up to 5–7.5×10$^{34}$ cm$^{-2}$s$^{-1}$. This High Luminosity upgrade of the LHC (HL-LHC) will deliver a total of 3000–4000 fb-1 of proton-proton collisions at a center-of-mass energy of 13–14 TeV. To cope with these challenging environmental conditions, the strip tracker of the CMS experiment will be upgraded using modules with two closely-spaced silicon sensors to provide information to include tracking in the Level-1 trigger selection. This paper describes the performance, in a test beam experiment, of the first prototype module based on the final version of the CMS Binary Chip front-end ASIC before and after the module was irradiated with neutrons. Results demonstrate that the prototype module satisfies the requirements, providing efficient tracking information, after being irradiated with a total fluence comparable to the one expected through the lifetime of the experiment