General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

Design and test of the final ALICE SDD CARLOS end ladder board

The paper presents the design and test of the final prototype of the CARLOS (Compression And Run Length Encoding Subsystem) end ladder board that is going to be used in the ALICE experiment at CERN. This board is able to compress data coming from one Silicon Drift Detector (SDD) front-end electronics and to send them towards the data concentrator card CARLOSrx in counting room via a 800 Mb/s optical link. The board design faces several constraints, mainly size (54x49 mm) and radiation tolerance: for this reason the board contains several CERN developed ASICs. A test setup has been realized for selecting the good devices among the 500 cards already produced

A comparison of AMPV subtypes A and B full genomes, gene transcripts and proteins led to reverse-genetics systems rescuing both subtypes

Avian metapneumovirus (AMPV) infection of poultry causes serious disease in most countries and subtype A reverse-genetic (RG) systems have allowed a generation of viruses of known sequence, and proved useful in developments towards better control by live vaccines. While subtype B viruses are more prevalent, bacterial cloning issues made subtype B RG systems difficult to establish. A molecular comparison of subtype A and B viruses was undertaken to assess whether subtype A RG components could be partially or fully substituted. AMPV subtype A and B gene-end sequences leading to polyadenylation are, to our knowledge, reported for the first time, as well as several leader and trailer sequences. After comparing these alongside previously reported gene starts and protein sequences, it was concluded that subtype B genome copies would be most likely rescued by a subtype A support system, and this assertion was supported when individual subtype A components were successfully substituted. Application of an advanced cloning plasmid permitted eventual completion of a fully subtype B RG system, and proved that all subtype-specific components could be freely exchanged between A and B systems

The Silicon Drift Detector readout scheme for the Inner Tracking System of the ALICE Experiment

Presentation at Quark Matter '99, Torino, Italy, 10-15 May 1999The Silicon Drift Detectors (SDDs) provide, through the measurement of the drift time of the charge deposited by the particle which crosses the detector, information on the impact point and on the energy deposition. The foreseen readout scheme is based on a single chip implementation of an integrated circuit that includes low-noise amplification, fast analog strorage and analog to digital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buffer that reduces the transmission bandwidth and a data compression/zero suppression unit complete the architecture.Abstract:In this paper, the system components design is described, together with the results of the first prototypes

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS

Multiplicity dependence of jet-like two-particle correlations in p-Pb collisions at sNN\sqrt{s_{NN}} = 5.02 TeV

Two-particle angular correlations between unidentified charged trigger and associated particles are measured by the ALICE detector in p-Pb collisions at a nucleon-nucleon centre-of-mass energy of 5.02 TeV. The transverse-momentum range 0.7 $< p_{\rm{T}, assoc} < p_{\rm{T}, trig} <$ 5.0 GeV/$c$ is examined, to include correlations induced by jets originating from low momen\-tum-transfer scatterings (minijets). The correlations expressed as associated yield per trigger particle are obtained in the pseudorapidity range $|\eta|<0.9$. The near-side long-range pseudorapidity correlations observed in high-multiplicity p-Pb collisions are subtracted from both near-side short-range and away-side correlations in order to remove the non-jet-like components. The yields in the jet-like peaks are found to be invariant with event multiplicity with the exception of events with low multiplicity. This invariance is consistent with the particles being produced via the incoherent fragmentation of multiple parton--parton scatterings, while the yield related to the previously observed ridge structures is not jet-related. The number of uncorrelated sources of particle production is found to increase linearly with multiplicity, suggesting no saturation of the number of multi-parton interactions even in the highest multiplicity p-Pb collisions. Further, the number scales in the intermediate multiplicity region with the number of binary nucleon-nucleon collisions estimated with a Glauber Monte-Carlo simulation.Comment: 23 pages, 6 captioned figures, 1 table, authors from page 17, published version, figures at http://aliceinfo.cern.ch/ArtSubmission/node/161

A simulation tool for MRPC telescopes of the EEE project

The Extreme Energy Events (EEE) Project is mainly devoted to the study of the secondary cosmic ray radiation by using muon tracker telescopes made of three Multigap Resistive Plate Chambers (MRPC) each. The experiment consists of a telescope network mainly distributed across Italy, hosted in different building structures pertaining to high schools, universities and research centers. Therefore, the possibility to take into account the effects of these structures on collected data is important for the large physics programme of the project. A simulation tool, based on GEANT4 and using GEMC framework, has been implemented to take into account the muon interaction with EEE telescopes and to estimate the effects on data of the structures surrounding the experimental apparata.A dedicated event generator producing realistic muon distributions, detailed geometry and microscopic behavior of MRPCs have been included to produce experimental-like data. The comparison between simulated and experimental data, and the estimation of detector resolutions is here presented and discussed

Effective Rheology of Bubbles Moving in a Capillary Tube

We calculate the average volumetric flux versus pressure drop of bubbles moving in a single capillary tube with varying diameter, finding a square-root relation from mapping the flow equations onto that of a driven overdamped pendulum. The calculation is based on a derivation of the equation of motion of a bubble train from considering the capillary forces and the entropy production associated with the viscous flow. We also calculate the configurational probability of the positions of the bubbles.Comment: 4 pages, 1 figur

Recent Developments on the Silicon Drift Detector readout scheme for the ALICE Inner Tracking System

Proposal of abstract for LEB99, Snowmass, Colorado, 20-24 September 1999Recent developments of the Silicon Drift Detector (SDD) readout system for the ALICE Experiment are presented. The foreseen readout system is based on 2 main units. The first unit consists of a low noise preamplifier, an analog memory which continuously samples the amplifier output, an A/D converter and a digital memory. When the trigger signal validates the analog data, the ADCs convert the samples into a digital form and store them into the digital memory. The second unit performs the zero suppression/data compression operations. In this paper the status of the design is presented, together with the test results of the A/D converter, the multi-event buffer and the compression unit prototype.Summary:In the Inner Tracker System (ITS) of the ALICE experiment the third and the fourth layer of the detectors are SDDs. These detectors provide the measurement of both the energy deposition and the bi-dimensional position of the track. In terms of readout an SDD can be viewed as a matrix, where the rows are the detector anodes and the columns are the samples to be read during the drift time; therefore, a very large amount of data has to be amplified, converted in digital form and preprocessed in order to avoid the storage of non-significatn data.Since the electron mobility is a strong temperature function, detector temperature has to be kept constant; on the other hand, it is not possible to use very efficient cooling systems because the amount of material in this area is very limited, so the power budget for the electronic readout is very low (less than 6 mW/anode).The simplest solution would be to send the analog signals outside the sensitive area immediately after a preamplification; unfortunately, the ratio between the number of channels (around 200 000) and the space available is so high that the simple solution of sending all the SDD anodes output outside teh detector zone after a low-noise amplification is not practically manageable.Abstract:The adopted solution is based on three main units:(i) A front-end chip that performs low noise amplification, fast analog storage and A/D conversion(ii) A multi-event digital buffer for data derandomization(iii) A data compression/zero suppression and system control boardThe first two units are distributed on the ladders near the detectors and have stringent power and space requirements, while the third unit is placed at both ends of the ladders and in boxes placed on both ends of the TPC detector.The first unit is the most critical part of the system. It works as follows: the detector signals are continuously amplified, sampled and stored in the analog memory with a frequency of 40 MSamples/s The L0d trigger signal stops the write operation, while the L1 trigger signal starts the conversion phase. This phase will continue until the event data are stored in the event buffer if the L2y confirm trigger signal is received, or rejected if the L2n abort signal will be issued by the trigger system.Prototypes of the three parts have been designed and tested while the full chip is currently under design. Tests of the A/D converter will be presented.The multi-event buffer purpose is to de-randomize the even data in order to reduce the transmission speed. Preliminary tests of the first prototype will be presented.The board placed at the end of the ladders performs various functions. It reduces the amount of data through various cascaded algorithms with variable parameters and transmits the data to the SIU board. It also controls the test and slow control system for the ladder circuitry. Tests of the FPGA-based prototypes will be presented.Special care has been taken for the test problem. The ASICs designed are provided of a test control port based on teh IEEE 1149.1 JTAG standard. The same protocol is used for downloading configuration information