Clinical phenotypes and constipation severity in Parkinson’s disease: Relation to Prevotella species

Background: The gut microbiome is speculated to play a crucial role in its pathogenesis of Parkinson’s disease as a triggering factor. Recent hypotheses suggested that Prevotella species regulate gut permeability, exert a neuroprotective effect, and interestingly, has been suspected to be deficient in PD patients, and so may play a role in this disease. Aim: This study was designed to compare between PD patients and their healthy controls as regards relative Prevotella abundance, prevalence of Prevotella-dominant Enterotype, and constipation severity. Also, to correlate Prevotella changes with the clinical phenotypes and  severity of motor and non-motor symptoms of PD. Methods: Twenty-five PD cases were enrolled in this study and cross-matched to 25 healthy subjects representing the control group. Overall NMS severity was assessed using the Non-Motor Symptoms Scale (NMSS). Quantitative SYBR green Real Time PCR was performed for the identification and quantitation of Prevotella in stool. Results: Prevotella relative abundance was 4-fold decreased in cases when compared to controls with PIGD phenotype showing the lowest abundance, however the difference was not statistically significance. Prevotella-dominant Enterotype was less presented in cases compared to controls, the result was statistically significant. Severe and very severe constipation grades presented 64% of cases group Vs 12% of control group. There was statistically significant positive correlation between total constipation score and UPDRS total score and motor symptoms phenotypes. Conclusion: Relative low Prevotella abundance in PD patients appears to be related to severe phenotypes of the disease; PIGD and mixed phenotypes. Severe constipation was more presented in PD cases which may be considered  as a preclinical biomarker for PD

High mobility SiMOSFETs fabricated in a full 300mm CMOS process

The quality of the semiconductor–barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the device quality. For devices fabricated in a full complementary metal oxide semiconductor (CMOS) process and of very thin oxide below a thickness of 10 nm, we report a record mobility of 17.5 × 103 cm2 V−1 s−1 indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving insight into further material optimization for large scale quantum processors

Low charge noise quantum dots with industrial CMOS manufacturing

Silicon spin qubits are among the most promising candidates for large scale quantum computers, due to their excellent coherence and compatibility with CMOS technology for upscaling. Advanced industrial CMOS process flows allow wafer-scale uniformity and high device yield, but off the shelf transistor processes cannot be directly transferred to qubit structures due to the different designs and operation conditions. To therefore leverage the know-how of the micro-electronics industry, we customize a 300mm wafer fabrication line for silicon MOS qubit integration. With careful optimization and engineering of the MOS gate stack, we report stable and uniform quantum dot operation at the Si/SiOx interface at milli-Kelvin temperature. We extract the charge noise in different devices and under various operation conditions, demonstrating a record-low average noise level of 0.61 ${\mu}$eV/${\sqrt{Hz}}$ at 1 Hz and even below 0.1 ${\mu}$eV/${\sqrt{Hz}}$ for some devices and operating conditions. By statistical analysis of the charge noise with different operation and device parameters, we show that the noise source can indeed be well described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured MOS spin qubits as a mature and highly scalable platform for high fidelity qubits.Comment: 22 pages, 13 figure

Reducing the environmental impact of surgery on a global scale: systematic review and co-prioritization with healthcare workers in 132 countries

Abstract Background Healthcare cannot achieve net-zero carbon without addressing operating theatres. The aim of this study was to prioritize feasible interventions to reduce the environmental impact of operating theatres. Methods This study adopted a four-phase Delphi consensus co-prioritization methodology. In phase 1, a systematic review of published interventions and global consultation of perioperative healthcare professionals were used to longlist interventions. In phase 2, iterative thematic analysis consolidated comparable interventions into a shortlist. In phase 3, the shortlist was co-prioritized based on patient and clinician views on acceptability, feasibility, and safety. In phase 4, ranked lists of interventions were presented by their relevance to high-income countries and low–middle-income countries. Results In phase 1, 43 interventions were identified, which had low uptake in practice according to 3042 professionals globally. In phase 2, a shortlist of 15 intervention domains was generated. In phase 3, interventions were deemed acceptable for more than 90 per cent of patients except for reducing general anaesthesia (84 per cent) and re-sterilization of ‘single-use’ consumables (86 per cent). In phase 4, the top three shortlisted interventions for high-income countries were: introducing recycling; reducing use of anaesthetic gases; and appropriate clinical waste processing. In phase 4, the top three shortlisted interventions for low–middle-income countries were: introducing reusable surgical devices; reducing use of consumables; and reducing the use of general anaesthesia. Conclusion This is a step toward environmentally sustainable operating environments with actionable interventions applicable to both high– and low–middle–income countries

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications

Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-Tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-Temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-Temperature data at 295K to 4K and 40mK data.</p

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications

Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-Tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-Temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-Temperature data at 295K to 4K and 40mK data.</p