CliCTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16 x 128 elongated pixels, each measuring 300 x 30 μm$^{2}$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented

20-ps resolution Clock Distribution Network for a fast-timing single photon detector

The time resolution of active pixel sensors whose timestamp mechanism is based on Time-to-Digital Converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The Clock Distribution Network that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew), and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated Clock Distribution Network that fulfills these requirements is presented for the FastICpix single photon detector ¿ aiming at a 65nm process. A 40 MHz master clock is distributed to 64x64 pixels over an area of 2.4x2.4 cm2 using digital Delay-Locked Loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution

Design and characterisation of the CLICTD pixelated monolithic sensor chip

A novel monolithic pixelated sensor and readout chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the Compact Linear Collider (CLIC), and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of 16×128 elongated channels, each measuring 300×30 μm2. Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit Time-of-Arrival (with 10 ns time bins) and 5-bit Time-over-Threshold measurement is performed on the combined digital output of the 8 sub-pixels in every channel. The chip has been fabricated in two process variants and characterised in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e‾ and a noise of about 14 e‾ RMS. The design aspects and characterisation results of the CLICTD chip are presented

Detector Technologies for CLIC

The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It is foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. It offers a rich physics program including direct searches as well as the probing of new physics through a broad set of precision measurements of Standard Model processes, particularly in the Higgs-boson and top-quark sectors. The precision required for such measurements and the specific conditions imposed by the beam dimensions and time structure put strict requirements on the detector design and technology. This includes low-mass vertexing and tracking systems with small cells, highly granular imaging calorimeters, as well as a precise hit-time resolution and power-pulsed operation for all subsystems. A conceptual design for the CLIC detector system was published in 2012. Since then, ambitious R&D programmes for silicon vertex and tracking detectors, as well as for calorimeters have been pursued within the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector requirements with innovative technologies. This report introduces the experimental environment and detector requirements at CLIC and reviews the current status and future plans for detector technology R&D.Comment: 152 pages, 116 figures; published as CERN Yellow Report Monograph Vol. 1/2019; corresponding editors: Dominik Dannheim, Katja Kr\"uger, Aharon Levy, Andreas N\"urnberg, Eva Sickin

The Compact Linear Collider (CLIC) - 2018 Summary Report

The Compact Linear Collider (CLIC) is a TeV-scale high-luminosity linear $e^+e^-$ collider under development at CERN. Following the CLIC conceptual design published in 2012, this report provides an overview of the CLIC project, its current status, and future developments. It presents the CLIC physics potential and reports on design, technology, and implementation aspects of the accelerator and the detector. CLIC is foreseen to be built and operated in stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. CLIC uses a two-beam acceleration scheme, in which 12 GHz accelerating structures are powered via a high-current drive beam. For the first stage, an alternative with X-band klystron powering is also considered. CLIC accelerator optimisation, technical developments and system tests have resulted in an increased energy efficiency (power around 170 MW) for the 380 GeV stage, together with a reduced cost estimate at the level of 6 billion CHF. The detector concept has been refined using improved software tools. Significant progress has been made on detector technology developments for the tracking and calorimetry systems. A wide range of CLIC physics studies has been conducted, both through full detector simulations and parametric studies, together providing a broad overview of the CLIC physics potential. Each of the three energy stages adds cornerstones of the full CLIC physics programme, such as Higgs width and couplings, top-quark properties, Higgs self-coupling, direct searches, and many precision electroweak measurements. The interpretation of the combined results gives crucial and accurate insight into new physics, largely complementary to LHC and HL-LHC. The construction of the first CLIC energy stage could start by 2026. First beams would be available by 2035, marking the beginning of a broad CLIC physics programme spanning 25-30 years

CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a $180$ nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of ${16\times128}$ elongated pixels, each measuring ${300\times30}$ $\mu$m$^2$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous $8$-bit time measurement with $10$ ns time bins and $5$-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented.The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16 × 128 elongated pixels, each measuring 300 × 30 μm$^2$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented

New architecture for the analog front-end of Medipix4

The Medipix4 chip is the latest member of the family of Medipix pixel detector readout chips aimed at high rate spectroscopic X-ray imaging. Unlike its predecessors, it will be possible to tile the chip on all 4 sides permitting seamless large area coverage. This paper focuses on the development of the new Medipix4 front-end architecture capable of event-by-event data processing allowing accurate photon energy reconstruction, with charge sharing correction at an increased rate compared to Medipix3. The architecture is particularly well adapted for readout of pixelated high-Z detector materials allowing accurate energy binning of incoming hits at a fine pixel pitch. The new front-end architecture has a linear response up to 150 keV (CdTe), a count-rate capability up to 5.1×10$^{8}$ photons.mm$^{−2}$s$^{−1}$ for 10% dead time loss at 10 keV (CdTe) , and an energy resolution aiming for 2.2 keV FWHM (Full Width Half Maximum) at 60 keV (CdTe). The layout accommodates sensors with either 70μm or 140μm pitch of contacts

Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging

Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm$^2$/sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm$^2$. The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm$^2$ while preserving high rate capability