The CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nm imaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in the context of the CLIC tracking detector study, comprises a matrix of 16 x 128 elongated pixels, each measuring 300 x 30 μm$^{2}$. To ensure prompt charge collection, every elongated pixel is segmented in eight sub-pixels, each containing a collection diode and a separate analog front-end. A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement with programmable range is performed in the on-pixel digital logic. The main design aspects as well as the first results from laboratory measurements with the CLICTD chip are presented

Ballabriga, R.

Dort, K.

Egidos, N.

Kremastiotis, I.

Munker, M.

English

KITopen

CLICTD: A monolithic HR-CMOS sensor chip for theCLIC silicon trackerI. Kremastiotis * a,b, R. Ballabriga a, K. Dort a,c, N. Egidos a,d , M. Munker aon behalf of the CLICdp collaborationaCERN, Geneva, SwitzerlandbKarlsruhe Institute of Technology, Karlsruhe, GermanycJustus-Liebig-Universitaet Giessen, Giessen, GermanydUniversity of Barcelona, Barcelona, SpainE-mail: iraklis.kremastiotis@cern.chThe CLIC Tracker Detector (CLICTD) is a monolithic pixelated sensor chip produced in a 180 nmimaging CMOS process built on a high-resistivity epitaxial layer. The chip, designed in thecontext of the CLIC tracking detector study, comprises a matrix of 16×128 elongated pixels,each measuring 300×30 µm2. To ensure prompt charge collection, every elongated pixel issegmented in eight sub-pixels, each containing a collection diode and a separate analog front-end.A simultaneous 8-bit time measurement with 10 ns time bins and 5-bit energy measurement withprogrammable range is performed in the on-pixel digital logic. The main design aspects as wellas the first results from laboratory measurements with the CLICTD chip are presented.Topical Workshop on Electronics for Particle Physics2 - 6 September 2019Santiago de Compostela, Spain*Speaker.© Copyright owned by the author(s) under the terms of the Creative CommonsAttribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND 4.0). https://pos.sissa.it/arXiv:2004.02537v1  [physics.ins-det]  6 Apr 2020CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker I. Kremastiotis1. IntroductionA novel monolithic pixel sensor chip, the CLIC Tracker Detector (CLICTD), is presented.The CLICTD chip features a matrix of 128 rows and 16 columns with pixels of 300× 30 µm2.The chip was designed according to the requirements for the silicon tracker at the future CompactLinear Collider (CLIC) [1]. These requirements include a Time of Arrival (ToA) measurementwith 10 ns time bins, and a 5-bit Time over Threshold (ToT) measurement for time walk correc-tion. Moreover, the 5-bit ToT measurement (which has a programmable range from 0.6 to 4.8 µs)enables a precise hit position interpolation that is needed to reach a single point resolution of 7 µmalong the transverse plane with the pitch of 30 µm. Other requirements include a total materialbudget of 1− 1.5% X0 per detection layer (allowing for ∼ 200 µm for the silicon layers) and anaverage power consumption below 150 mW/cm2. In order to minimise the average analog powerconsumption, the analog front-end can be set to a standby power mode in the 20 ms gaps betweensubsequent colliding bunch trains (power pulsing), taking advantage of the low duty cycle of theCLIC beam [2]. The digital power consumption is minimised by means of clock gating. Details onthe CLICTD chip design have been presented in [3].2. Process descriptionThe design was implemented in a 180 nm High-Resistivity (HR) CMOS imaging process,where a deep P-well is used in order to shield the on-pixel electronics from the collection electrode.The signal is collected with a small area N-well on top of a P-type high resistivity epitaxial layer.This results in a small capacitance (a few fF) for the collection electrode and helps to minimise theanalog power consumption and the noise in the front-end. Full depletion of the epitaxial layer isachieved by including an additional deep N-type implant. Two different pixel layouts were imple-mented and manufactured through a process split on different wafers. As illustrated in Figure 1,the first pixel layout is with a continuous deep N-type implant, and the second with a segmenteddeep N-type implant to increase the lateral field and thereby reduce the charge collection time [4].In addition, reduced charge sharing is expected because of the gap in the N-implant. The gap isintroduced only along the long dimension of the pixel, as the short pixel dimension correspondsto the transverse detector plane, where charge sharing can be beneficial for improving the positionresolution through hit position interpolation.nwell pwelldeep pwelllow dose n-type implantcollec on electrodep- epitaxial layerp+ substrateVPWELLVSUB(a)nwell pwelldeep pwelllow dose n-type implantcollec on electrodep- epitaxial layerp+ substrateVPWELLVSUB(b)Figure 1: The two process splits: (a) continuous N-implant, and (b) gap in N-implant (not to scale).3. The CLICTD prototype chipThe CLICTD matrix comprises 16× 128 elongated pixels of 300× 30 µm2. Each pixel issegmented in eight sub-pixels, each with its individual collection diode and analog front-end, to1CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker I. Kremastiotis-800-600-400-200 0 200 400 600 800 0  5  10  15  20I PWELL [uA]V SUB [-V]PWELL: -1 VPWELL: -2 VPWELL: -3 VPWELL: -4 VPWELL: -5 VPWELL: -6 VCLICdp -preliminary(a)-800-600-400-200 0 200 400 600 800 0  5  10  15  20I PWELL [uA]V SUB [-V]PWELL: -1 VPWELL: -2 VPWELL: -3 VPWELL: -4 VPWELL: -5 VPWELL: -6 VCLICdp -preliminary(b)Figure 2: Leakage current measured at the P-wells in the CLICTD matrix as a function of thesubstrate bias, for different values of the P-well bias. CLICTD sample from (a) the first processoption - continuous N-implant, and (b) the second process option - gap in N-implant.ensure prompt charge collection. The diodes are therefore spaced by 37.5 µm along the long pixeldirection. Every front-end includes level shifter, voltage amplifier, discriminator and a 3-bit localthreshold tuning DAC. The level shifter acts as a unity gain buffer and is placed as close to thecollection electrode as possible to minimise the input capacitance. One bit indicating whether thefront-end detected a particle is stored for each sub-pixel, while the simultaneous 8-bit ToA and 5-bitToT measurement is performed in the on-pixel digital logic for the combined output (by means ofan "OR" gate) of all eight discriminator outputs. Thus, the time-stamp of the first hit and the integralToT of all hits within the same frame are read out for each pixel. A serial readout at 40 MHz isemployed. To reduce the amount of data shifted out of the chip, a compression algorithm is applied.The data acquired during the frame are shifted out only for pixels that detected a particle. For pixelsthat did not detect a particle, only one bit is shifted out.4. Measurement resultsOnce fabricated, the CLICTD chip was characterised using the CaRIBOu readout system [5].4.1 I-V characteristicThe sensor bias operation range was determined by measuring its I-V characteristics. Theleakage current at the P-wells in the pixel area (biased at VPWELL in Figure 1) was measured, whilescanning the substrate bias voltage, and for given values of the P-well bias ranging from −1 to−6 V. The region where the leakage current remains stable and relatively low (< 20 µA for thefull chip) is the region where the sensor can be operated (marked in red in Figure 2). For the firstpixel layout in Figure 1a, the continuous deep N-type implant offers a better isolation between theP-wells and the substrate. Therefore, the substrate can be biased to a higher (in absolute value)voltage, as shown in Figure 2a. Due to the reduced isolation originating from the gap in the deepN-type implant in the second pixel layout, the sensor can be operated only when the two nodes arebiased at a similar voltage level (Figure 2b), a result which is in agreement with simulations [4].4.2 Noise measurements and equalisationDuring the threshold equalisation for the CLICTD pixel matrix, the baseline for each sub-pixelis extracted as the mean value of the curve produced after scanning the threshold and counting thenumber of noise hits for each threshold. In order to equalise the matrix on a sub-pixel basis, the2CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker I. Kremastiotis3500400030002500200015001000  500     0120 130 140 150 160 170 180 190# pixels Pixel BaselineThreshold [DAC code]CLICdp -preliminaryCLICdp -preliminaryCLICdp -preliminaryCLICdp -preliminaryTuning DACs 0 (min.)Tuning DACs 7 (max.)Tuning DACs Equalised(a)Pixel Noise40000.560008000# pixels     0200031.5 2.5 21 0Threshold [DAC code]CLICdp -preliminary(b)Figure 3: (a) Distribution of pixel baselines obtained from threshold scans before (blue, red) andafter (green) equalisation. (b) Histogram of noise RMS per sub-pixel, in threshold DAC codes.scan was performed for each of the eight sub-pixels in the pixel, while the rest of the sub-pixelswere masked. The threshold scans were performed for the lowest and highest code of the 3-bitthreshold tuning DAC in the front-end. A linear interpolation was applied in order to select theDAC codes for which the threshold dispersion over the matrix is minimised. Figure 3a presents thethreshold scan for lowest (blue curve), highest (red curve) and equalised (green curve) DAC code.A histogram of the noise RMS per sub-pixel, extracted in threshold DAC codes as the RMS valueof the curve resulting from the threshold scan for each sub-pixel, is plotted in Figure 3b. Based onthe threshold DAC step to electrons conversion extracted in Section 4.3, the threshold dispersionfor the equalised CLICTD matrix is about 25 e− and the mean value of the noise RMS is 13 e−.The above results are from a CLICTD sample with gap in the n-layer, with both the P-wells andthe substrate biased to −2 V.4.3 Measurements with radiation sourcesFigure 4a presents the fluorescence spectra from an iron (red curve) and a copper (blue curve)target, measured with the CLICTD chip using an X-ray beam. The CLICTD threshold was scannedduring this measurement and the number of detected photons was stored in each pixel and read outfor every threshold. The produced occupancy curve gives the number of counts above threshold, foreach applied threshold step. For a given beam intensity and frame duration, this number dependson the fluorescence emission spectrum of the target. A differentiation of the occupancy curve givesthe measured energy spectrum.From the mean values of the Gaussian fits for the Kα peaks for iron (6.4 keV) and copper(8.04 keV), and with an electron-hole pair creation energy in silicon of 3.62 eV, the LSB of thethreshold DAC has been extracted to correspond to ∼ 16 e−. The minimum detectable charge forthe chip settings applied for this measurement is estimated to be ∼ 300 e−.Using the same setup, an X-ray image of a small item (screw) was taken with the CLICTDchip. The image presented in Figure 4b was produced with 1000 acquisitions of 4 ms shutter length,with equalised matrix. The number of frames when a hit was detected is plotted for each sub-pixel.For the above measurements, a CLICTD sample with continuous N-implant was used, whilethe reverse bias was set to −2 V at the P-wells and to −4 V at the substrate. The sensor capaci-tance (and consequently the front-end performance) strongly depends on the sensor bias [6]. The3CLICTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker I. Kremastiotis500  1000  1500  2000  2500  3000                                                                 Threshold [e-]050001000015000 Iron TargetCopper TargetDerivative of # countsCLICdp -preliminary(a)  0           20          40          60          80         100        120         0Columns20406080100120Rows200300400500600700100 8009001000(b)Figure 4: (a) Fluorescence spectra using iron (red) and copper (blue) targets, measured with theCLICTD chip. (b) X-ray image of a screw, recorded with the CLICTD chip.front-end was biased at its default values after chip reset and the operation parameters were not yettuned for signal-to-noise performance. Under these bias conditions, the analog part of the matrixconsumes ∼170 mW/cm2, while the on-pixel digital logic consumes another 240 mW/cm2. Theexpected average power consumption of the CLICTD matrix over the cycle of the CLIC acceler-ator, as extrapolated from static power measurements and simulated values, is ∼5 mW/cm2, afterapplying the power pulsing scheme introduced in Section 1. In addition, 43 mW are consumed bythe analog and digital periphery electronics.5. SummaryA monolithic sensor chip, the CLIC Tracker Detector (CLICTD), designed in the frameworkof the CLIC silicon tracker study, has been presented. The chip was produced in a modified CMOSimaging process and features a novel architecture with segmented pixels. Preliminary results showa threshold dispersion of 25 e− and a mean noise RMS of 13 e− over the CLICTD matrix, afterthreshold equalisation. The average power consumption over the CLIC beam cycle is estimated tobe ∼5 mW/cm2 for the pixel matrix, plus 43 mW for the periphery electronics.AcknowledgementsThis project has received funding from the European Union’s Horizon 2020 research and in-novation programme under grant agreement No 654168.References[1] D. Dannheim, A. Nurnberg, Requirements for the CLIC tracker readout, CLICdp-Note-2017-002.2017.[2] Physics and Detectors at CLIC: CLIC Conceptual Design Report,edited by L. Linssen, A. Miyamoto, M. Stanitzki, H. Weerts, CERN-2012-003. 2012.[3] I. Kremastiotis et al., Design of a monolithic HR-CMOS sensor chip for the CLIC silicon tracker,CLICdp-Conf-2018-008. 2018.[4] M. Munker et al., Simulations of CMOS pixel sensors with a small collection electrode, improved fora faster charge collection and increased radiation tolerance, JINST 14 C05013. 2019.[5] A. Fiergolski, A multi-chip data acquisition system based on a heterogeneous system-on-chipplatform, CLICdp-Conf-2017-012. 2017.[6] M. Munker, Test beam and simulation studies on High Resistivity CMOS pixel sensors,CERN-THESIS-2018-202. 2018.4

CliCTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

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CliCTD: A monolithic HR-CMOS sensor chip for the CLIC silicon tracker

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