Multistage System High-Speed Clock Difficulty in VLSI

Abstract A Multi-Synchronization (MS) write-in shared buffer switch architecture is presented for a multistage system to relieve clock timing difficulty on various length connection links between switch elements in ultra high speed VLSI. The above architecture is useful to obtain flexibility and feasibility of VLSI design at sub nsec pulse switching because 30 mm deference in linking wire length on a system VLSI chip gives more than 100 psec delay deference. A necessary buffer size for covering the design difficulty is evaluated by computer simulation. It is shown that a buffer size as same as that of a practical switch only is required for MS switch to ensure a same level with a performance of an ideal Single Synchronization (SS) write-in switch.