Image-guided multisession radiosurgery of skull base meningiomas

Background: The efficacy of single-session stereotactic radiosurgery (sSRS) for the treatment of intracranial meningioma is widely recognized. However, sSRS is not always feasible in cases of large tumors and those lying close to critically radiation-sensitive structures. When surgery is not recommended, multi-session stereotactic radiosurgery (mSRS) can be applied. Even so, the efficacy and best treatment schedule of mSRS are not yet established. The aim of this study is to validate the role of mSRS in the treatment of skull base meningiomas. Methods: A retrospective analysis of patients with skull base meningiomas treated with mSRS (two to five fractions) at the University of Messina, Italy, from 2008 to 2018, was conducted. Results: 156 patients met the inclusion criteria. The median follow-up period was 36.2 \ub1 29.3 months. Progression-free survival at 2-, 5-, and 10-years was 95%, 90%, and 80.8%, respectively. There were no new visual or motor deficits, nor cranial nerves impairments, excluding trigeminal neuralgia, which was reported by 5.7% of patients. One patient reported carotid occlusion and one developed brain edema. Conclusion: Multisession radiosurgery is an effective approach for skull base meningiomas. The long-term control is comparable to that obtained with conventionally-fractionated radiotherapy, while the toxicity rate is very limited

n-XYTER: A CMOS read-out ASIC for a new generation of high rate multichannel counting mode neutron detectors

For a new generation of 2-D neutron detectors developed in the framework of the EU NMI3 project DETNI [1], the 128-channel frontend chip n-XYTER has been designed. To facilitate the reconstruction of single neutron incidence points, the chip has to provide a spatial coordinate (represented by the channel number), as well as time stamp and amplitude information to match the data of x- and y-coordinates. While the random nature of the input signals calls for self-triggered operation of the chip, on-chip derandomisation and sparsi cation is required to exploit the enormous rate capability of these detectors ( 4 106cm2s1). The chosen architecture implements a preampli er driving two shapers with di erent time constants per channel. The faster shaper drives a single-pulse discriminator with subsequent time-walk compensation. The output of this circuit is used to latch a 14-bit time stamp with a 2 ns resolution and to enable a peak detector circuit fed by the slower shaper branch. The analogue output of the peak detector as well as the time stamp are stored in a 4-stage FIFO for derandomisation. The readout of these FIFOs is accomplished by a token-ring based multiplexer working at 32 MHz, which accounts for further derandomisation, sparsi cation and dynamic bandwidth distribution. The chip was submitted for manufacturing in AMS's C35B4M3 0.35µm CMOS technology in June 2006

Metastatic mixed gestational trophoblastic tumour of the uterus: A case report

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Visualization of the joining of ribosomal subunits reveals the presence of 80S ribosomes in the nucleus

In eukaryotes the 40S and 60S ribosomal subunits are assembled in the nucleolus, but there appear to be mechanisms preventing mRNA binding, 80S formation, and initiation of translation in the nucleus. To visualize association between ribosomal subunits, we tagged pairs of Drosophila ribosomal proteins (RPs) located in different subunits with mutually complementing halves of fluorescent proteins. Pairs of tagged RPs expected to interact, or be adjacent in the 80S structure, showed strong fluorescence, while pairs that were not in close proximity did not. Moreover, the complementation signal is found in ribosomal fractions and it was enhanced by translation elongation inhibitors and reduced by initiation inhibitors. Our technique achieved 80S visualization both in cultured cells and in fly tissues in vivo. Notably, while the main 80S signal was in the cytoplasm, clear signals were also seen in the nucleolus and at other nuclear sites. Furthermore, we detected rapid puromycin incorporation in the nucleolus and at transcription sites, providing an independent indication of functional 80S in the nucleolus and 80S association with nascent transcripts

CMOS pixel sensor development: a fast read-out architecture with integrated zero suppression

International audienceCMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010

Production test of microstrip detector and electronic frontend modules for the STAR and ALICE trackers

We revisit Shin et al.’s leakage-resilient password-based authenticated key establishment protocol (LR-AKEP) and the security model used to prove the security of LR-AKEP. By refining the Leak oracle in the security model, we show that LR-AKE (1) can, in fact, achieve a stronger notion of leakage-resilience than initially claimed and (2) also achieve an additional feature of traceability, not previously mentioned

A ten thousand frames per second readout MAPS for the EUDET beam telescope

Designed and manufactured in a commercial CMOS 0.35 μm OPTO process for equipping the EUDET beam telescope, MIMOSA26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels with 576 rows and 1152 columns, covering an active area of ~224 mm2. A single point resolution of about 4 μm was obtained with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The paper describes the chip design, test and major characterisation outcome