We revisit Shin et al.’s leakage-resilient password-based authenticated key establishment protocol (LR-AKEP) and the security model used to prove the security of LR-AKEP. By refining the Leak oracle in the security model, we show that LR-AKE (1) can, in fact, achieve a stronger notion of leakage-resilience than initially claimed and (2) also achieve an additional feature of traceability, not previously mentioned

Lutz, Jean Robert

Arnold, L

Baudot, J

Bonnet, D

Coffin, J P

Germain, M

Gojak, C

Guedon, M

Hippolyte, B

Kühn, C E

Suire, C

Tarchini, A

Berst, D

Brogna, A

Clauss, G

Colledani, C

Deptuch, G

Hu, C

Boucham, A

Bouvier, S

Drancourt, C

Erazmus, B

Guilloux, G

Janik, M

Peryt, W

Radomski, S

Szarwas, P

M. Bellare

R. Canetti

K.-K.R. Choo

H. Fathi

G. Itkis

S.-H. Shin

Crossref

Security of a Leakage-Resilient Protocol for Key Establishment and Mutual Authentication

CERN Document Server

PRODUCTION TESTS OF MICROSTRIP DETECTOR AND ELECTRONICFRONTEND MODULES FOR THE STAR AND ALICE TRACKERSJ.R. Lutz*, L. Arnold, J. Baudot, D. Bonnet,J.P. Coffin, M. Germain, C. Gojak, M. Guedon, B. Hippolyte, C. Kuhn, C. Suire, A. TarchiniInstitut de Recherches Subatomiques - IReS - IN2P3/ CNRS - ULPBP28, F 67037 Strasbourg Cedex 02 - FranceD. Berst, A. Brogna, G. Clauss, C. Colledani, G. Deptuch, C. HuLaboratoire d’Electronique et de Physique des Systèmes Instrumentaux LEPSI - IN2P3/CNRS - ULPBP28, F 67037 Strasbourg Cedex 02 - FranceA. Boucham, S. Bouvier, C. Drancourt, B. Erazmus, G. GuillouxLaboratoire de Physique Subatomique et des Technologies Associées SUBATECHBP20722, F 44307 Nantes Cedex 03 – FranceM. Janik, W. Peryt, S. Radomski, P. SzarwasWarsaw University of Technology, Faculty of Physics, Warsaw - Polandand the STAR collaboration, and the ALICE collaboration*Contribution presented at LEB2000 in Krakòw, Poland, by Jean-Robert.Lutz@ires.in2p3.frAbstractA compact front-end microstrip detector module hasbeen designed and prototyped. It includes a Double-Sided(DS) Silicon Strip Detector (SSD) and the related FrontEnd Electronics (FEE) located on two hybrids, one for theN side and one for the P side [1]. Bumpless TapeAutomated Bonding (TAB) [2], [3], [4] is used to connectthe detector to the dedicated ALICE128C FE chip [5], [6],[7] located on the hybrids by means of microcables. Thesemicrocables are bent in order to fold over the two hybridson the DS SSD. This module meets the specifications oftwo experiments, ALICE (A Large Ion ColliderExperiment) at the LHC collider at CERN [8], [9] andSTAR (Solenoid Tracker At Rhic) at the RHIC collider atBNL (Brookhaven National Laboratory) [10]. This self-consistent FE module has been tested in the PS and SPSbeams at CERN for signal, noise and resolution and inthe Vivitron beam for radiation hardness. The relatedresults have been presented [1], [9], [11]. At present, theproduction of these modules is starting for the STARexperiment whereas the corresponding production forALICE belongs to a near future. Careful controls and testsare essential at each production step as described in thisreport.1. INTRODUCTIONThe STAR SSD layer overlaying the Silicon VertexTracker (SVT) requires 320 working detector modules i.e.the production of a total of 400 modules. The ALICEInternal Tracker System (ITS) requires 1700 similarmodules i.e. the production of more than 1800. The verylow power consumption of these modules allows air-cooling in STAR but water-cooling has been kept inALICE, representing the only significant technicaldifference between the two applications.Whereas the tested prototype modules have been mainlymanufactured inside the laboratory, production of morethan a few units must be transferred to industry.Manufacturing such a module relates to three maintasks: producing the components of the module,assembling these components and testing each componentand subassembly after each step as displayed in figure 1.All the test results are transferred to a production data basewhich provides network access to the data for the wholecollaboration by means of any net browser at the webaddress    http://star.in2p3.fr  and/or    http://ssd.if.pw.edu.pl  .Fig. 1: Manufacturing and testing of a module.Each module is a mechanically self-consistent assemblyof one DS SSD and two FEE hybrids, connected togetherby TABed microcables.Each of these FEE hybrids includes a flex cable, part ofthe hybrid in charge of interconnecting active and passivecomponents on the hybrid, the stiffener supporting theflex cable, the passive electronic SMD components, theALICE128C FE chips, the COSTAR control chip [12].2. DOUBLE SIDED SSDThe 75 ×  42 ×  0.3 mm DS SSD includes 768 ACcoupled strips on each side with a pitch of 95µm at astereoscopic angle of 35 mrad. Guard and bias rings areall together ≤ 1 mm wide.Production specifications have been described in theCCTP document [13]. The main features relate to aunique operating voltage below 55 volts in betweendepletion voltage and breakdown voltage, a biasing currentibias ≤ 2µA, a guard ring leakage current iguard ≤ 5µA,and a number of dead coupling capacitors on each sidebelow or equal to 10.More than 440 detectors have been delivered by Eurisysand tested in our laboratory on a probe station in order toselect 400 detector working inside the specifications. Thetest itself is done by mounting the bare detector in anepoxy frame (figure 2) which enables handling,identification, and connection to the test equipment forbiasing by means of two bonds on each side. This frameand the related bonds are removed later before the moduleassembling step. The test measurements are transferredinto the production data base.Fig. 2: Measurement of a DS SSD in it's frame.2.1  Operating voltage and currentThe operating voltage Vop is derived from the operatingrange defined between the depletion voltage Vd and thebreakdown voltage Vbd defined as the biasing voltagecorresponding to the maximum allowed current. Deepinvestigation has been made in order to define those in areliable way. Depletion voltage Vd can be investigated bymeasuring, as a function of biasing voltage, the biascurrent ibias, the bulk capacitance Cbulk, the bulk resistivityρbulk and the interstrip capacitance Cinterstrip, on the N side.Figure 3 shows itotal = ibias + iguard = f(V) in black,1/C2bulk = f(V) in blue and ρbulk = f(V) in red.The itotal = f(V) graph shows a weak slope in theplateau area due to the nominal guard ring leakage. The1/C interstrip N = f(V) graph (not represented) shows thesame plateau as the itotal = f(V) graph.Fig. 3: Operating range of DS SSD STAR171.The same detector has been assembled in a module andconnected to the front-end electronics. Noisemeasurements of the strips provide also a goodinformation on the depletion. Figure 4 shows theitotal = f(V) graph in black squares and the RMS noisegraph in red dots. They all show the same plateau for thesame voltage range.Fig. 4: Total current and noise as a function of voltage.So, it has been demonstrated that the only itotal = f(V)measurement provides consistent and exhaustiveinformation on ibias, iguard, Vd, Vbd, and Vop.Figure 5 represents the number of detectors as afunction of their possible operating voltage. This plot ismade by considering a detector as "1" inside the operatingrange and as "0" outside this range and adding togetherthese values over the whole set of measured detectors.This graph shows that about 75% of the detectors cantheoretically be operated with a unique common biasingvoltage of 53 volts. Once the Vop has been defined, onecan measure the corresponding operating total current itotwhose mean value 1.65 µA appears in figure 6.ito tal = f(V)ρbulk = f(V)Fig. 5: Sum of the operating ranges of 332 detectors.Fig. 6: Total current  itot: mean = 1.65µA2.2 Coupling capacitorsThe FEE is located on two separate but identical hybrids,one connected to the N side and one to the P side of thedetector by means of capacitors integrated on top of eachstrip for AC coupling. Dielectric characteristics of theinsulation, i.e. leakage current and capacitance, areobviously important for detection efficiency and dataconsistency. Measuring both leakage current andcapacitance enables cross checking, the latter alsovalidating the contact quality. During thesemeasurements, a DC voltage of 100 V is applied acrossthe capacitor to check if it stands the operating voltage.These parameters are measured for each strip by steppingthrough the contact pads with a test probe. This optionavoids all the switching and probe card problems withouttaking significant more time yet. The corresponding dataare registered in the data base. The related distributions arepresented on figure 7 left for the P side and right for the Nside. A capacitor is considered as dead if it leaks or if thecapacitance is out of range. The mean number of deadcapacitors is below 2 units on both sides. 85% of the DSSSDs have at most 4 dead capacitors on both sides i.e.less than about 0.5% of the 768 strips of each detectorside.Fig. 7: Dead capacitors on P side (left) and N side (right)2.3 Detector qualityCompiling the results of these different measurementsprovides a global information about the quality of theproduced detectors as presented on table 1.Class Quality Nb. of SSDs %1 Perfect 258 65%2 Good 74 18%3 >10 dead strips/side 20 5%4 High currents 14 3%5 Dead 20 5%6 Vd > 55V 13 3%7 To be tested again 1 /Table 1: Quality of the 400 measured DS SSD.2.4 Strip leakage currentFor production, we consider that theitotal = ibias + iguard = f(V) measurement  described in 2.1and the coupling capacitor measurement described in 2.2are consistent to characterize a detector. We chose to avoidany disturbance of the main detector by DC test pads. Ifneeded, it is possible to measure the strip leakage currenton a test structure located on the same wafer as the realdetector. It should be below 5 nA/strip. Furthermore, ifthe number of leaking strips becomes significant, theproblem is detected by the measurement of ibias. So, thestrip leakage current is not measured in production,mainly for throughput reasons.3. ALICE128C FRONT-END CHIPEach detector module includes two FE hybridsincluding each 6 FE ALICE128C chips [1], [3], [9]. Soproducing 400 detector modules for STAR (320 on theexperiment + spares) requires 12x400=4800 workingchips. 6000 tested chips have been ordered at AMS, thetest being a rough test made on the wafer. After cutting,sorting in boxes and TABing of these chips ontomicrocables, they are measured again in our laboratorybefore sending for TABing onto the hybrids and detectors.Testing of these chips has been made easy by integratinginside the chip, from the design level, JTAG operatedremote access to all the digital and analog parameters andalso to a programmable on-chip pulse generator for eachanalog channel [14].3.1 Manufacturer production and test on waferFrom 6000 tested production chips ordered at AMS, wegot 5656 "good" chips, 5355 "bad" inked chips havingbeen rejected by the rough wafer tests.3.2 The use of microcablesThe TABed microcables, providing electrical connectionbetween the DS SSD and the FE chips and between theFE chips and the hybrid, allow for a mechanical freedomin the positioning of the hybrids supporting the FE chipsversus the detector. Au layered Cu microcables (17 µmCu on top of 70 µm Kapton) are used for STAR [3]whereas Al microcables (14 µm Al on top of 12 µmKapton) will be used for ALICE [4]. Their use eases alsothe chip test and avoids the use of the probe station.3.3 Laboratory test of the TABed chipsThe accurate testing of these chips is then made at thelaboratory after TABing of the chips onto microcables andmounting them in a plastic tests frame for easy handlingand testing. So, the chip in its plastic carrier [3] plugseasily into the test socket of the automated chip testequipment presented in figure 8. The overall duration ofthe automated test is below 5 minutes per chip. The testresults are recorded into the production database for lateruse.The test includes 7 main steps.• Power the chip and check "+i" and "–i" which shouldboth be negligible.• Test the digital part of the chip by means of JTAG.• Bias the chip by sending via JTAG the 7 analogoperating parameters.• Check again "+i" which should stay at about theprevious level and "–i" which should increase by20 mA.• By means of JTAG, switch one analog channel totransparent mode, pulse it with the on-chip pulsegenerator and register the sampled analog positive andnegative output.• With "0" input, make acquisition of the 128 channelsfor pedestal registration.• With the on-chip pulse generator, pulse sequentiallyeach analog channel with positive and negative pulseswith values of +100, +250, -100 and –250 andregister the corresponding outputs.The measurement of 87 TABed production chipsprovided 83 good chips and 5 bad ones including 1 withovercurrent, 1 with 24/128 dead channels 2 with 2 deadchannels and 1 with 1 dead channel. Plots of the otherparameters are not represented as they present a verynarrow dispersion around the nominal value. The 94%yield after the wafer tests corresponds mainly to cutting,handling  and TABing.Fig. 8: ALICE128C chip automated test equipment4. COSTAR CONTROL CHIPThe COSTAR control chip has been designed forremote JTAG monitoring and control of various analogand digital parameters [15]. Basic feature includes on-chiptemperature measurement, which is especially importantfor air-cooling, and on-chip power supply voltagemeasurement. It includes also detector guard and biascurrent monitoring. One COSTAR is located on eachSTAR hybrid.Testing of the COSTAR bare chip is performed on theprobe station by means of a probe card and an automatedtest equipment. Calibrating of the on-chip temperaturesensor is performed during the same process. Results areprovided to the production data base. From 351 testedchips, 311 are "good" and 40 "rather bad".5. THE ASSEMBLED MODULEThe test of the 400 assembled modules for STAR and1800 for ALICE requires automation and optimizing. Thebasic aims are to get inside the data base, the operatingparameters and location of each channel of each module.This includes an automated diagnosis of all the channels,the identification and location of each disturbed channelfor any reason and the characteristics of the workingchannels in terms of gain and also of on-chip pulsegenerator calibration.The defective channels can suffer from noise mainlyrelated to a leaking strip, they may be shorted togetherwith their neighbor, they may not be connected, theymay be connected to a strip with a dead couplingcapacitor, they correspond to a dead amplifier channeleither with a dead input (blocked channel) or with a deadamplifying chain.For diagnosis, one gets the inputs from the productiondata base corresponding to the measurements made on thecomponents before assembling. One also pulses theamplifiers for testing them "in-situ" by means of theDUTJTAG operated on-chip programmable pulse generator. Inthe test equipment developed at IReS, we systematicallypulse also the whole detector chain by means of a pulselight source scanning the surface of the detector toproduced located calibrated charges inside the detector.After deconvolution, the information coming from the• components tests recovered from the data base,• noise acquisitions,• on-chip pulse generator acquisition and• light pulse acquisition of the triggered detectoris cross-checked for a very accurate diagnosis of theassembled detector modules and finally, the diagnosisresults are again stored into the data base. Figure 9 showsthis test equipment, the Device Under Test (DUT) beinginside the black box for protection against external light.Fig. 9: The automated module test equipment.To achieve this goal, full control and data acquisitionare required for the module  as well as opto-insulation ofthe electronics connected to the floating side and alsomotion control of the light source.6. CONCLUSIONThe existing TABed DS SSD modules have beenpreviously validated for their main characteristics onvarious beam tests, focused on geometric resolution,signal to noise ratio [1], [9] and radiation hardness [11].Now, for producing these modules, a set of automated testbenches has been developed for the various tests at thedifferent steps of assembling, of the components as wellas sub-assemblies, complete modules and soon completeladders supporting a number of modules. Their operationefficiency has been demonstrated. They are now applied tothe STAR modules. On the ALICE detector modules,slight changes have been made. The DS SSD strip angleshave been slightly changed to +7.5 and –27.7 mradinstead of ±17.5 mrad to minimize the ambiguityproblem, a new HAL25 hardened FE chip has beendesigned and the ALICE modules have to meet the water-cooling requirements. Adapting the existing testequipments to the ALICE detector module should implyminor changes only.REFERENCES[1] J.R. Lutz et al., “Detector and front end electronics forALICE and STAR silicon strip layers”,CERN/LHCC/98-36, Proceedings of the 4th workshop onelectronics for LHC experiments, Rome, September 1998[2] S. Bouvier et al., “ TAB packaging technology for theSi-strip front end detector assembly ”, Proc. of the 4thworkshop on electronics for LHC experiments, Rome,September 21-25, 1998[3] J.R. Lutz et al., “TAB bonded SSD module for theSTAR and ALICE trackers”, CERN/LHCC/99-33,Proceedings of the 5th workshop on electronics for LHCexperiments, Snowmass, Co, USA, September 1999.[4] A.P. de Haas, A. van den Brick, P. Kuijer,C.J. Oskamp NIKHEF, Utrecht, V.N. Borshchov,S.K. Kiprich, V.M. Ruzhitsky SRTIIM, Kharkov”Very low mass microcables for the ALICE silicon stripdetector” Proceedings of LEB99, 1999.[5] L. Hébrard et al., “ALICE128C: A CMOS FullCustom ASIC for the Readout of Silicon Strip Detectorsin the ALICE Experiment ”, Proc. of the third workshopon electronics for LHC experiments, Imperial College,London, September 22-26, 1997, pp. 173-177[6] L. Hébrard et al., “Electrical characterization ofALICE128C: a low-power CMOS ASIC for the readoutof Silicon Strip Detectors”, CERN/LHCC/98-36,Proceedings of the 4th workshop on electronics for LHCexperiments, Rome, September 21-25, 1998[7] L. Hébrard, J.P. Blondé, C. Colledani, G. Clauss,“Design and Test of a CMOS Low-Power Mixed-Analog/Digital ASIC for Radiation Detector ReadoutFront Ends ”, Proc. of the 11th Annual IEEEInternational ASIC Conference, ASIC’98, Rochester,New York, September 13-16, 1998.[8] “ALICE: Technical Proposal for A Large Ion ColliderExperiment at the CERN LHC ”, CERN/LHCC/95-71,LHCC/P3, December 1995[9] “ALICE ITS Technical Design Report”,CERN/LHCC 99-12[10] “Proposal for a Silicon Strip Detector for STAR”,SUBATECH, IReS, LEPSI, France, Wayne StateUniversity, USA, 1998[11] M. Germain et al., “Irradiation of a Silicon StripDetector and readout chips for the ALICE experiment atLHC”, NIM A 434 (1999) 345.[12] J.D. Berst, C. Colledani, “ COSTAR”, COSTARNote V0.1-LEPSI 9904 (April 1999).[13] J.R. Lutz, S. Bouvier, "Cahier des ClausesTechniques Particulières": Fabrication de deux lots dedétecteurs à micro-pistes au silicium, (January 1999)[14] H. Bleeker, P. Van den Eijnden and F. De Jong,“ BOUNDARY SCAN TEST - A Practical Approach ”,Kluwer Academic Publishers, 1993[15] D. Bonnet et al “ Control system of the siliconmicrostrip layer for the STAR experiment”, Proceedingsof ICALEPS'99 Trieste, (October 4-8 1999).DUT

Production test of microstrip detector and electronic frontend modules for the STAR and ALICE trackers

Production test of microstrip detector and electronic frontend modules for the STAR and ALICE trackers

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