Eager Stack Cache Memory Transfers

The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program\u27s worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. The stack cache, for instance, allows the compiler to efficiently cache a program\u27s stack, while static analysis of its behavior remains easy. This work introduces an optimization of the stack cache that allows to anticipate memory transfers that might be initiated by future stack cache control instructions. These eager memory transfers thus allow to reduce the average-case latency of those control instructions, very similar to "prefetching" techniques known from conventional caches. However, the mechanism proposed here is guaranteed to have no impact on the worst-case execution time estimates computed by static analysis. Measurements on a dual-core platform using the Patmos processor and imedivision-multiplexing-based memory arbitration, show that our technique can eliminate up to 62% (7%) of the memory transfers from (respectively to) the stack cache on average over all programs of the MiBench benchmark suite

Worst-Case Execution Time Analysis of Predicated Architectures

The time-predictable design of computer architectures for the use in (hard) real-time systems is becoming more and more important, due to the increasing complexity of modern computer architectures. The design of predictable processor pipelines recently received considerable attention. The goal here is to find a trade-off between predictability and computing power. Branches and jumps are particularly problematic for high-performance processors. For one, branches are executed late in the pipeline. This either leads to high branch penalties (flushing) or complex software/hardware techniques (branch predictors). Another side-effect of branches is that they make it difficult to exploit instruction-level parallelism due to control dependencies. Predicated computer architectures allow to attach a predicate to the instructions in a program. An instruction is then only executed when the predicate evaluates to true and otherwise behaves like a simple nop instruction. Predicates can thus be used to convert control dependencies into data dependencies, which helps to address both of the aforementioned problems. A downside of predicated instructions is the precise worst-case execution time (WCET) analysis of programs making use of them. Predicated memory accesses, for instance, may or may not have an impact on the processor\u27s cache and thus need to be considered by the cache analysis. Predication potentially has an impact on all analysis phases of a WCET analysis tool. We thus explore a preprocessing step that explicitly unfolds the control-flow graph, which allows us to apply standard analyses that are themselves not aware of predication

Alignment of Memory Transfers of a Time-Predictable Stack Cache

N/AModern computer architectures use features which often com-plicate the WCET analysis of real-time software. Alterna-tive time-predictable designs, and in particular caches, thus are gaining more and more interest. A recently proposed stack cache, for instance, avoids the need for the analysis of complex cache states. Instead, only the occupancy level of the cache has to be determined. The memory transfers generated by the standard stack cache are not generally aligned. These unaligned accesses risk to introduce complexity to the otherwise simple WCET analysis. In this work, we investigate three different ap-proaches to handle the alignment problem in the stack cache: (1) unaligned transfers, (2) alignment through compiler-gen-erated padding, (3) a novel hardware extension ensuring the alignment of all transfers. Simulation results show that our hardware extension offers a good compromise between average-case performance and analysis complexity

Parallel Copy Elimination on Data Dependence Graphs

Register allocation regained much interest in recent years due to the development of decoupled strategies that split the problem into separate phases: spilling, register assignment, and copy elimination. Traditional approaches to copy elimination during register allocation are based on interference graphs and register coalescing. Variables are represented as nodes in a graph, which are coalesced, if they can be assigned the same register. However, decoupled approaches strive to avoid interference graphs and thus often resort to local recoloring. A common assumption of existing coalescing and recoloring approaches is that the original ordering of the instructions in the program is not changed. This work presents an extension of a local recoloring technique called Parallel Copy Motion. We perform code motion on data dependence graphs in order to eliminate useless copies and reorder instructions, while at the same time a valid register assignment is preserved. Our results show that even after traditional register allocation with coalescing our technique is able to eliminate an additional 3% (up to 9%) of the remaining copies and reduce the weighted costs of register copies by up to 25% for the SPECINT 2000 benchmarks. In comparison to Parallel Copy Motion, our technique removes 11% (up to 20%) more copies and up to 39% more of the copy costs

Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis

The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program\u27s worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. A stack cache, for instance, allows the compiler to efficiently cache a program\u27s stack, while static analysis of its behavior remains easy. Likewise, its implementation requires little hardware overhead. This work introduces an optimization of the standard stack cache to avoid redundant spilling of the cache content to main memory, if the content was not modified in the meantime. At first sight, this appears to be an average-case optimization. Indeed, measurements show that the number of cache blocks spilled is reduced to about 17% and 30% in the mean, depending on the stack cache size. Furthermore, we show that lazy spilling can be analyzed with little extra effort, which benefits the worst-case spilling behavior that is relevant for a real-time system

Efficient Context Switching for the Stack Cache: Implementation and Analysis

International audienceThe design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that has been proven to provide good average-case performance, while being easy to analyze.So far, however, the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved and restored when a task is preempted.We propose (a) an analysis exploiting the simplicity of the stack cache to bound the overhead induced by task preemption and (b) an extension of the design that allows to (partially) hide the overhead by virtualizing stack caches

Arbitration-Induced Preemption Delays

The interactions among concurrent tasks pose a challenge in the design of real-time multi-core systems, where blocking delays that tasks may experience while accessing shared memory have to be taken into consideration. Various memory arbitration schemes have been devised that address these issues, by providing trade-offs between predictability, average-case performance, and analyzability. Time-Division Multiplexing (TDM) is a well-known arbitration scheme due to its simplicity and analyzability. However, it suffers from low resource utilization due to its non-work-conserving nature. We proposed in our recent work dynamic schemes based on TDM, showing work-conserving behavior in practice, while retaining the guarantees of TDM. These approaches have only been evaluated in a restricted setting. Their applicability in a preemptive setting appears problematic, since they may induce long memory blocking times depending on execution history. These blocking delays may induce significant jitter and consequently increase the tasks\u27 response times. This work explores means to manage and, finally, bound these blocking delays. Three different schemes are explored and compared with regard to their analyzability, impact on response-time analysis, implementation complexity, and runtime behavior. Experiments show that the various approaches behave virtually identically at runtime. This allows to retain the approach combining low implementation complexity with analyzability

GIS-Based Mapping of Ecosystem Services: The Case of Coral Reefs

This chapter illustrates the process of mapping ecosystem service values with an application to coral reef recreational values in Southeast Asia. The case study provides an estimate of the value of reef-related recreation foregone, due to the decline in coral reef area in Southeast Asia, under a baseline scenario for the period 2000 – 2050. This value is estimated by combining a visitor model, meta-analytic value function and spatial data on individual coral reef ecosystems to produce site-specific values. Values are mapped in order to communicate the spatial variability in the value of coral reef degradation. Although the aggregated change in the value of reef-related recreation due to ecosystem degradation is not high, there is substantial spatial variation in welfare losses, which is potentially useful information for targeting conservation efforts

Acriflavine, a clinically approved drug, inhibits SARS-CoV-2 and other betacoronaviruses

The COVID-19 pandemic caused by SARS-CoV-2 has been socially and economically devastating. Despite an unprecedented research effort and available vaccines, effective therapeutics are still missing to limit severe disease and mortality. Using high-throughput screening, we identify acriflavine (ACF) as a potent papain-like protease (PLpro) inhibitor. NMR titrations and a co-crystal structure confirm that acriflavine blocks the PLpro catalytic pocket in an unexpected binding mode. We show that the drug inhibits viral replication at nanomolar concentration in cellular models, in vivo in mice and ex vivo in human airway epithelia, with broad range activity against SARS-CoV-2 and other betacoronaviruses. Considering that acriflavine is an inexpensive drug approved in some countries, it may be immediately tested in clinical trials and play an important role during the current pandemic and future outbreaks. © 2021 The Author

Glioneuronal tumor with ATRX alteration, kinase fusion and anaplastic features (GTAKA): a molecularly distinct brain tumor type with recurrent NTRK gene fusions

Glioneuronal tumors are a heterogenous group of CNS neoplasms that can be challenging to accurately diagnose. Molecular methods are highly useful in classifying these tumors-distinguishing precise classes from their histological mimics and identifying previously unrecognized types of tumors. Using an unsupervised visualization approach of DNA methylation data, we identified a novel group of tumors (n = 20) that formed a cluster separate from all established CNS tumor types. Molecular analyses revealed ATRX alterations (in 16/16 cases by DNA sequencing and/or immunohistochemistry) as well as potentially targetable gene fusions involving receptor tyrosine-kinases (RTK; mostly NTRK1-3) in all of these tumors (16/16; 100%). In addition, copy number profiling showed homozygous deletions of CDKN2A/B in 55% of cases. Histological and immunohistochemical investigations revealed glioneuronal tumors with isomorphic, round and often condensed nuclei, perinuclear clearing, high mitotic activity and microvascular proliferation. Tumors were mainly located supratentorially (84%) and occurred in patients with a median age of 19 years. Survival data were limited (n = 18) but point towards a more aggressive biology as compared to other glioneuronal tumors (median progression-free survival 12.5 months). Given their molecular characteristics in addition to anaplastic features, we suggest the term glioneuronal tumor with ATRX alteration, kinase fusion and anaplastic features (GTAKA) to describe these tumors. In summary, our findings highlight a novel type of glioneuronal tumor driven by different RTK fusions accompanied by recurrent alterations in ATRX and homozygous deletions of CDKN2A/B. Targeted approaches such as NTRK inhibition might represent a therapeutic option for patients suffering from these tumors