Aportaciones a la historia de la transmisión de la Consolatio ad Liviam

Tras algunas cuestiones relativas a una edición de la Consolatio ad Liviam, damos noticia por vez primera de dos nuevos excerpta y de una edición incunable de la misma, y restituimos una conjetura a su legítimo autorAfter some questions relating to an edition of Consolatio ad Liuiam, we present for the first time two new excerpts and incunable which edits it, and restore a conjecture to its rightful autho

Vacvvs, vidvvs, solvs, desertvs, relictvs en Catulo, Propercio y Tibulo

El autor trata de probar que existe una relación especial y estrecha entre los términos del título cuando los poetas mencionados los emplean para describir el abandono amatorio, la ausencia o la soledad del amante o del amado, y piensa que esto está apoyado, sobre todo, por Prop. 1 18._____________________________ The author tries to prove that there is a special and tight relationship between the words of the title when the mentioned poets use them to describe the amatory abandonment, absence or solitude of the lover or the beloved, and thinks it is supported, mainly, by Prop. I 18

Indefessae labor limae Sepulvedanae en los libros 19 y 20 de la De rebus gestis Caroli quinti historia

Los dos manuscritos sepulvedanos de la Historia de Carlos V contienen distintas anotaciones y correcciones del propio autor, que a lo largo de su vida retocó una y otra vez su magna obra. Se estudian las diversas fases de la intervención del autor en los manuscritos y se dilucidan los motivos de los cambios introducidos, fundamentalmente con vistas a ajustarse a la latinitas y a conseguir una mayor claridad en la narración, además de un estilo más depurado

Estacio, Tebaida I 214-218: una oculta alusión al cíclope Pyracmon

We highlight the poetic technique of etymological wordplay with proper names in Statius and argue that in Theb. I 218 the poet alludes to Cyclops Pyracmon by the expression incudibus ignes.Ponemos de relieve la técnica poética del juego de palabras etimológico con los nombres propios en Estacio y defendemos que en Theb. I 218 el poeta alude al cíclope Pyracmon mediante la expresión incudibus ignes

Desde Calímaco a Cervantes: una imagen venatoria en contexto amatorio

The image of the hunter going after the escaping prey and scorning that one caught, in an amatory context (the lover is the hunter going after the escaping beloved, leaving the woman he has already conquered), starts from Callimachus and goes to Cervantes, who probably should take it not from classical sources, but from Ariosto’s Orlando Furioso. The image offers different applications, depending on the authors who employ it.La imagen del cazador que persigue la presa que huye y deja la que atrapa, dentro de un contexto amatorio (el enamorado es el cazador que persigue a la amada huidiza, abandonando a la que ya ha conseguido), se inicia con Calímaco y llega hasta Cervantes, quien la tomaría no de las fuentes clásicas, sino del Orlando Furioso de Ariosto. La imagen adquiere diversas aplicaciones, según los autores que la utilizan

Las notas a Catulo de A. Petreius y N. Heinsius (Berol. Diez. oct. 2474)

In this paper we collect the textual corrections and conjectures made to the text of Catullus by A. Petreius and N. Heinsius, many of them based on previous codices, editions and scholars, gathered on a copy of the editio Aldina of 1515, now Berol. Diez. oct. 2474, and also Heinsius’s notes in his Adversariorum libri IV.En este artículo reunimos las correcciones y conjeturas hechas al texto de Catulo por A. Petreius y N. Heinsius, basadas muchas de ellas en códices, ediciones y filólogos anteriores y reunidas en un ejemplar de la edición aldina de 1515, hoy Berol. Diez. oct. 2474, y también las notas de Heinsius en sus Adversariorum libri IV

Modeling of Real Bistables in VHDL

A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented niodel provides very realistic information about the device behavior, which until now had to be obtained through electric simulation

Inertial and Degradation Delay Model for CMOS Logic Gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches

New CMOS VLSI Linear Self-Timed Architectures

The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear selftimed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two nbit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise