The authors present the Inertial and Degradation
Delay Model (IDDM) for CMOS digital simulation. The
model combines the Degradation Delay Model presented in
previous papers with a new algorithm to handle the inertial effect,
and is able to take account of the propagation and filtering
of arbitrarily narrow pulses (glitches, etc.). The model clearly
overcomes the limitations of conventional approaches

Acosta Jiménez, Antonio José

Bellido Díaz, Manuel Jesús

Juan Chico, Jorge

Ruiz de Clavijo Vázquez, Paulino

Valencia Barrero, Manuel

English

idUS. Depósito de Investigación Universidad de Sevilla

ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland Inertial and Degradation Delay Model for CMOS Logic Gates ' J. Juan-Chico*, P. Ruiz de Clavijo", M. J. Bellido", A.J. Acosta**, M. Valencia* Instituto de Microelectrhica de Sevilla-CNM, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain *also with Departamento de Tecnologia Electr6nica (Univ. de Sevilla) **also with Departamento de Electr6nica y Electromagnetism0 (Univ. de Sevilla) e-mail: jjchico@ imse.cnm.es Abstract.- The authors present the Inertial and Degrada- tion Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ef- fect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches. I. INTRODUCTION Nowadays, the unique option for the timing verification of VLSI digital systems is the use of logic timing simulators, which allow us to explore the design space in a reasonable pe- riod of time. The main drawback of logic simulation is its lack of precision, which mainly depends on the timing models of the logic blocks implemented in the simulator. Better timing models mean better precision and higher confidence in the tim- ing verification of the circuit. New timing models for CMOS digital circuits have been recently proposed, specially during the last few years. All these models improve the accuracy of the simulation results by including effects such as the transi- tion slopes [I], carriers speed saturation in submicronic tech- nologies [2,3] or input collisions [4,5,6,7]. We are interested in modeling those input collisions that may generate glitches, and how these glitches are propagated through the circuit. Other authors have studied the problem [8, 91 but their models are not able to achieve a high degree of ac- curacy. Recently, a new model, called DDM, which handles the propagation of glitches has been presented [4,5]. The deg- radation effect is presented there, and basically causes the shortening of pulses as they are propagated through the gates. This model achieves a high degree of precision in the whole pulse widths range. A glitch or a pulse that is successively degraded, is likely to suffer the so called inertial effect [lo]. The inertial effect is re- sponsible for the filtering of narrow pulses that try to propagate through a logic gate. Until now, the inertial effect is taken into account by means of the definition of an inertial delay [lo]. We have observed that this model lacks accuracy, as we will see below. The main objective of this paper is to present the Inertial and Degradation Delay Model (IDDM), which combines the degradation effect with a new algorithm to handle the inertial effect. The result is a very accurate delay model that can deal with the propagation of pulses of any width and their elimina- tion. 11. DEGRADATION DELAY MODEL (DDM) Typical models for logic simulation only consider the iner- tial effect to deal with very narrow pulses. These models show discontinuous behavior for very similar input conditions. Un- like the actual behavior, this discontinuity is due to the fact that depending on its width, an input pulse may be in a normal propagation or a filtering (non-propagation) region. Neverthe- less, the change in the behavior of a true gate is not abrupt, rather continuous and gradual. In fact, two limit cases appear in real behavior: one for wide pulses that are propagated nor- mally and another for very narrow pulses that are eliminated, but there is a pulse-width range between them in which pulses are neither eliminated nor propagated normally. Inside this range, the output pulse width is smaller than the corresponding input pulse width. In such a case, the pulse is considered to be degraded. This effect has been postulated in [ 111, even though no practical model was developed in this work. Some other au- thors have studied the problem in order to account for glitch propagation and elimination [8,12]. A comparison of this mod- els can be found at [9]. These proposed solutions consider con- stant slope transition models which lead to a linear reduction in the propagation delay, as pulses are narrowed. On the contrary, we showed in [4,5] that the delay decreases exponentially as pulses are shortened. There, full degradation effect insights are studied for the case of a CMOS gate in, inverter operation and a delay model that takes account of the exponential behavior of the degradation effect is presented. We summarize some con- clusions: only two parameters for each type of transition, z 0-7803-5482-6/99/$10.00 '2000 IEEE 1-459 @) (a) Figure 1: Inertial delay model failure example: a) sample cir- cuit, b) DC curves of gl and 82. and T o ,  are needed to model the degradation effect, resulting in the following formula: where tpO is the normal propagation delay, that can be calcu- lated from a conventional delay model [3, 131, T is the time elapsed since the last output transition in the gate’s output, which measures the internal state of the gate, and T and To are the degradation parameters which depend on the gate’s internal geometry and environmental conditions (output load, input waveform and supply voltage). This model will be referred to as DDM (Degradation Delay Model). In. INERTIAL DELAY MODEL FAILURE The inertial effect is currently modeled through the defini- tion of an inertial delay. As stated in [lo]: “An inertial delay with magnitude Di behaves the same way as a pure delay, ex- cept that it not only delays the input signal by Di , but also fil- ters out positive or negative pulses of duration less than Di ”. This model is illustrated in Fig. 6.1 1 of [lo]. Most logic-timing simulators use an inertial delay to take the inertial effect into account. To calculate the value of the in- ertial delay of a given gate, the criteria widely adopted is the use of an universal (same for each gate) threshold voltage at half the supply rail ( VDD/2 ) to measure signal switching. In this way, an input pulse to a gate is filtered if the generated out- put pulse does not reach the VDD/2 threshold, and then, an in- put pulse of width smaller than Di generates an output pulse of amplitude smaller than VDD/2. This simple model is not accurate in many situations, as we will see next. In Fig. l a  we find a test circuit in which an inverting driver (go) is loaded by two other inverter gates, g l  and 82. The two loading inverters have different DC transfer curves with different threshold volt- ages: VT,= 1.32v, Vn= 3 . 4 1 ~  (Fig. lb). These thresholds are defined as the input voltages that makes VOut = VDD/2, which is good way to estimate the output logic state of the gate for a given input voltage, due to the large value of the slope at that point of the DC curves. Each loading inverter, in turn, is out2c 2 ’ outl outlc 0 in out0 outl out2 outlc out2c I I I I I I - I - I I I I - I I I I I I I I I . -  I I J I I - 0 1 2 3 (b) igure 2: Results for the sample circuit: a) HSPICE simulation, b) expected output of a logic simulator based on inertial delays. loaded by a chain of inverters, which are able to rei, yenerate positive pulses. The propagation of an input pulse at go, nar- rower than the inertial delay, is simulated using the electrical simulator HSPICE [ 141 and a conventional inertial delay mod- el. Results are plotted in Fig. 2. Obviously, as the pulse width is smaller than the inertial delay, the output pulse at outO does not reach the VD,/2 threshold and, from the point of view of a model using the inertial delay, the pulse is filtered a t  go and no other activity is observed in the logic simulation (Fig. 2b). On the contrary, the accurate electrical simulation in Fig. 2a shows that the output pulse at outO is able to propagate through g2 and is easily regenerated through the chain of tnverters (out2c), while it is filtered at g l .  That is, inertial effect only oc- curs for g l ,  but not for 82. This example shows how modeling the inertial effect through an inertial delay may predict an out- put result that differs from the actual behavior. The reason for this inaccuracy of the inertial delay model lies on that inertial effect cannot be accurately reproduced us- ing a single and universal threshold ( VDD/2 ) to determine logic switching. This way, pulses that do not reach the thresh- old, like the one at out0 in Fig. 2a, are neglected, while they are still able to propagate through a loading gate. Propagation of 1-460 such a pulse will depend on particular input thresholds of the loading gates. The pulse at out0 does not cross the input thresh- old of g l ,  as defined in the DC curves (Fig. lb), and then is not able to force out1 to switch; but the pulse crosses the input threshold of 82, so it will induce some change at 82 output, at least a small pulse like the one at out2, that might be regener- ated afterwards. It is clear then, that an accurate criterion to account for the inertial effect need to be based on signals crossing individual input thresholds. We propose a new model that combines the DDM to calcu- late delay and a new method to handle the inertial effect in or- der to take account of particular input thresholds. The new model is called Inertial and Degradation Delay Model (ID- DM) and is based on the following points: Signal transitions are approximated by linear ramps. The value of the ramp is calculated by the delay model. This ramps are represented by (thps,  z) pairs, where thps is the cross instant through the half power supply (V,,/2) and T is the transition time. Each transition at a given circuit node is split up in events, which corresponds to the signal cross through each input threshold of the gate's inputs connected to the node. The events are represented by ( tgt ,  z) pairs where rg t  is the cross instant through the input threshold and T is the tran- sition time. Given a transition, inertial effect is evaluated indepen- dently for each gate connected to the node as a function of the gate's input threshold and the events scheduled for that gate. The simulation algorithm that implements the IDDM must be driven by ( t g l ,  T) events instead of just signal transi- tions, since these events represents the actual gate's activa- tion instants. Delay models which measure delays between VDD/2 threshold crosses can easily be used with-this method since thps to tgt  conversions are carried out easily. As an example, Fig. 3 shows how the case in Fig. 1 is han- dled using this approach. In Fig. 3, transition-1 in signal out0 generates events gl-el and g2-el in g l  and g2 respectively. In the same way, transition-:! generates events g L e 2  and g2-e2. As the input threshold does not reach V,, , events gl-el and gl-e2 do not need to be evaluated, and will be dequeued before evaluation The IDDM can be summarized in the following simplified algorithm, which handles the propagation of an event given by a ( t g t ,  T) pair: - - - - - - - - / , \  0 - - 2 -  - \ - - -  Event generation using the proposed approach. Figure 3: 1. Calculate V,,/2 cross (thps(in) from ( tg , ,  T) . 2. Apply the DDM and calculate thps(out) and T(out ) .  3. For each gate input connected to the output of the gate under evaluation, do: Calculate event instant ( t )  from thps(out),   out) and the input threshold ( V, ). If the event happens after the last scheduled event ( t  > rlast ), schedule the new event; if not, dequeue event at Update tlnst: rlust  = t .  4. Grab a new event and continue. t1ast. V. RESULTS To check the performance of the inertial algorithm in ID- DM, we have applied the model to the case in Fig. 2. The waveforms that are generated using the IDDM are in Fig. 4. When compared to HSPICE results (Fig. 2a), the same behav- ior is obtained. The input pulse at in is not filtered, since it crosses go threshold. A small pulse at out0 is generated, which is large enough to activate 82, resulting in a propagation at out2 and a regeneration at out2c. On the other hand, the pulse at out0 does not reach g l  threshold, so it is filtered by g l  and no 50 r in _ _  00 50 0 .  r 2900 , 3900 _I out2 i outlc : out2c ; 3900 _I 3900 _I 00: IOW , ZWO , , 50 / I  low 2MO 00 ' 50 O ,  r IOW 2wo 3WO 00 t (PS) Figure 4: Waveforms generated using the proposed approach for the case in Fig. 2. 1-461 activity is observed in out1 and outlc. This example cannot be reproduced using a conventional inertial delay approach as we saw before (Fig. 2b). The next example shows a narrow pulse propagating through a multilevel combinational circuit which is represent- ed by a an inverter chain (Fig. 5). This example is useful to see in out1 out2 out3 Out4 Outs out6 out7 1 1 I 1 0 I 0 Figure 5: Narrow pulse propagating through an inverter chain. degradation and inertial effects working together. The solid soft lines corresponds to the HSPICE simulation, showing how the narrow pulse enters the chain and is degraded in each stage. Finally, it is eliminated due to inertial effect after stage 5. The piece-wise-linear solid lines corresponds to the simulation us- ing the IDDM, which almost match the HSPICE results up to the third stage (out3) and even give a good approximation in stages 4 and 5 when the pulse is degraded enough to loose its digital nature. As in HSPICE results, the pulse disappears in out6 and up. Finally, the dashed lines represents the results us- ing a conventional non-degraded model with transition slopes. In this case the pulse simply propagates unaltered through the whole chain, failing to show the quantitative and even the qual- itative behavior. VI. CONCLUSIONS The proposed model (IDDM) solves the problem of han- dling the propagation and filtering of arbitrarily narrow pulses through CMOS gates. It is based in the Degradation Delay Model previously presented [5] and in a new scheduling algo- rithm with is able to reproduce the inertial effect in a realistic way. The inertial effect is treated in a “per gate” basis, account- ing for particular input thresholds, while keeping the V,,/2 threshold convention for the delay evaluation, which is used by DDM and most delay models, and simplifies the gate charac- terization tasks. The IDDM simplifies the implementation and maintenance of the event queue during the simulation., since events are dequeued in the scheduling phase, not in the evalu- ation phase. Simulation results show a very good agreement with HSPICE simulations. For the sake of clarity, the case of narrow input pulses has been presented here, but the same method can be easily generalized to other types of input colli- sions that may also produce inertial effect. VII. REFERENCES [l] J.K. Ousterhout. “A Switch-Level Timing Verifier for Dig;ital MOS VLSI”. IEEE Trans. on CAD, Vol. CAD-4, No.3, pp. 336- 349. July 1985 [2] D. Auvergne, N. Azemard, R. Deschacht and M. Robert. ”Input Waveform Slope Effects in CMOS Delays”. IEEE J .  of Solid- State Circ., Vol. 25, No. 6, pp. 1588-1590. Dec. 1990 [3] L. Bisdounis, S .  Nikolaidis, 0. Koufopavlou. “Analytical Tran- sient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-Channel Devices”. IEEE J. of Solid-Sta.te Circ. pp. 302-306. Vol. 33, no. 2, Feb. 1998 [4] J.  Juan-chico, M.J. Bellido, A.J. Acosta, A. Barriga, M. Valencia. “Delay degradation effect in submicronic CMOS inverters”. In Proc. PATMOS’97. pp. 215-224. Louvain-la-Neuve, Belgium, 1997. [ 5 ]  M.J. Bellido, J.  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Huertas. “Metastable Operation in RS Flip-flops”. Int. J. Electronics, Vol. 70 n.6. 1991. [12]C. Metra, M. Favalli, B. Riccb. “Glitch power dissipation model”. In Proc. PATMOS’95. pp. 175-189 [13]J.M. Daga, S. Turgis, D. Auvergne. “Design Oriented Standard Cell Delay Modelling”. In Proc. PATMOS’96, pp. 265-274. [14]“HSPICE User‘s Manual”. Meta-software. 1996 MOS’96. pp. 167-176. 1-462 

Inertial and Degradation Delay Model for CMOS Logic Gates

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Inertial and Degradation Delay Model for CMOS Logic Gates

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