The implementation of digital signal processor circuits
via self-timed techniques is currently a valid altemative
to solve some problems encountered in synchronous
VLSI circuits. However; a main difference between synchronous
and asynchronous circuits is the hardware resources
needed to implement asynchronous circuits. This
communication presents four less-costly alternatives to a
previously reported linear selftimed architecture, and
their application in the design of FIFO memories. Furthermore,
the integration and characterization in the laboratory
of prototypes of these FIFOs are presented
