40-Gb/s TDM-PON downstream with low-cost EML transmitter and 3-level detection APD receiver

We report a cost-effective 40-Gb/s TDM-PON downstream utilizing an integrated DFB-EAM in OLT and an APD-based 3-level detection receiver in ONU, achieving a high power budget of 23.4 dB in real time operation

A 160Gb/s (4x40) WDM O-band Tx subassembly using a 4-ch array of silicon rings co-packaged with a SiGe BiCMOS IC driver

We present a 400 (8×50) Gb/s-capable RM-based Si-photonic WDM O-band TxRx with 1.17nm channel spacing for high-speed optical interconnects and demonstrate successful 50Gb/s-NRZ TxRx operation achieving a ~4.5dB Tx extinction ratio under 2.15Vpp drive

Multi-level optical signal generation using a segmented-electrode InP IQ-MZM with integrated CMOS binary drivers

We present a segmented-electrode InP IQ-MZM, capable of multi-level optical signal generation (5-bit per I/Q arm) by employing direct digital drive from integrated, low-power (1W) CMOS binary drivers. Programmable, multi-level operation is demonstrated experimentally on one MZM of the device

Demonstration of multi-channel 80 Gbit/s integrated transmitter and receiver for wavelength-division multiplexing passive optical network and fronthauling applications

The performance evaluation of a multi-channel transmitter that employs an arrayed reflective electroabsorption modulator-based photonic integrated circuit and a low-power driver array in conjunction with a multi-channel receiver incorporating a pin photodiode array and integrated arrayed waveguide grating is reported. Due to their small footprint, low power consumption and potential low cost, these devices are attractive solutions for future mobile fronthaul and next generation optical access networks. A BER performance of <10(-9) at 10.3 Gbit/s per channel is achieved over 25 km of standard single mode fibre. The transmitter/receiver combination can achieve an aggregate bit rate of 82.4 Gbit/s when eight channels are active

PAM-4 VCSEL driver with selective falling-edge pre-emphasis

Data centre optical links are migrating to four-level pulse amplitude modulation (PAM-4) as a method to extend the data rate while covering longer distances. Vertical-cavity surface-emitting lasers (VCSELs) enable the integration of low-power transmitters, but their non-linear and bias-dependent behaviour makes conventional feed-forward equalisation less effective. This Letter presents a 0.13 mu m SiGe BiCMOS PAM-4 driver that boosts the falling-edge to the bottom level through a selective pre-emphasis technique. Experiments at 25 GBd (50 Gb/s) reveal that adding selective pre-emphasis to a 4-tap equalised current driving a 20.6 GHz 1.5 mu m VCSEL, relaxes the critical PAM-4 link budget requirements by >1 dB at the KP4 forward error correction threshold of 2.2 x 10(-4). The potential of PAM-4 VCSEL transmitters can be significantly enhanced by including selective pre-emphasis to the equalisation topology while requiring minimal overhead

Spatial division multiplexing for optical data center networks

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A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time

Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conventional AC-coupled BM- RX has an inherent tradeoff between short settling time and decision threshold droop, which makes an RX settling time shorter than 400ns hard to achieve. Some techniques have been developed to overcome this limitation, demonstrating a settling time of 150 to 200ns. Our previous work uses feed-forward automatic offset compensation (AOC) to achieve a response time as short as 25.6ns. However, a feed-forward scheme using peak detectors is intrinsically less accurate and results in relatively high power consumption. In this paper, we present a DC-coupled 10Gb/s BM-TIA and burst-mode limiting amplifier (BM- LA) chipset that uses a feedback type AOC circuit with switchable loop BW. This new technique is capable of removing input DC offset in less than 75ns, and offers continuous decision threshold tracking during payload, to cope with the maximum length of CID. The differential TIA output port senses a CM reset signal provided by the succeeding BM-LA, and activates an on-chip reset and lock function. This BM-LA also integrates auto reset/activity generation circuits providing the AOC BW switching signal, so that this time-critical signal is not required from the PON system