Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration

International audienceSETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed

Data publication: CMOS-compatible manufacturability of sub-15 nm Si/SiO2/Si nanopillars containing single Si nanodots for single electron transistor applications

The data included in the publication are results of SET device simulations, Monte-Carlo simulations of physical processes (ion-beam mixing, phase seepration, Si nanodot formation) and micrographs taken by electron and ion microscopes

CMOS-compatible manufacturability of sub-15 nm Si/SiO2_2/Si nanopillars containing single Si nanodots for single electron transistor applications

International audienceThis study addresses the complementary metal-oxide-semiconductor-compatible fabrication of vertically stacked Si/SiO$_2$/Si nanopillars (NPs) with embedded Si nanodots (NDs) as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the NPs and NDs were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon ND formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiO$_x$ phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si ND self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si ND via phase separation within a confined SiO$_x$ disc of <500 nm$^3$ volume was experimentally validated. This work describes in detail the optimization of conditions required for NP/ND formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce NP diameter and for gate oxide fabrication whilst preserving the pre-existing NDs. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO$_2$/Si NP of 10 nm diameter, with tunnelling distances of about 1 nm between the Si ND and the neighboured Si regions forming drain and source of the SET