Does congenital deafness affect the structural and functional architecture of primary visual cortex?

Deafness results in greater reliance on the remaining senses. It is unknown whether the cortical architecture of the intact senses is optimized to compensate for lost input. Here we performed widefield population receptive field (pRF) mapping of primary visual cortex (V1) with functional magnetic resonance imaging (fMRI) in hearing and congenitally deaf participants, all of whom had learnt sign language after the age of 10 years. We found larger pRFs encoding the peripheral visual field of deaf compared to hearing participants. This was likely driven by larger facilitatory center zones of the pRF profile concentrated in the near and far periphery in the deaf group. pRF density was comparable between groups, indicating pRFs overlapped more in the deaf group. This could suggest that a coarse coding strategy underlies enhanced peripheral visual skills in deaf people. Cortical thickness was also decreased in V1 in the deaf group. These findings suggest deafness causes structural and functional plasticity at the earliest stages of visual cortex

The sources and sustainability of China's economic growth

Brookings Papers on Economic Activity21-6

Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications

The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL

ICTs and financial crime: an innocent fraud?

The democratizing dimension of the new information and communication technologies (ICTs) is a widely accepted proposition. Although this is repeatedly emphasized and explained by economic, political and social theories that deal with the analysis of the Information Society, a good deal of its significance has been systematically neglected. ICTs are exclusively approached either from the perspective of the globalization of knowledge or from the perspective of economic productivity. However, the democratizing role of ICTs includes an aspect that is far less treated yet more relevant: its ability to provide a greater transparency in the political, economical and social management of societies. This article describes the connection between the use of ICTs and financial crime; reports the fraud that, in the author’s opinion, is being created by means of ICTs, and claims the need of a greater attention for ICTs as a tool to fight the lack of transparency and white-collar crime