Orientación de la asignatura Sistemas Electrónicos Digitales al modelado de sistemas en VHDL partiendo de esquemas Matlab-Simulink

Versión extendida del texto publicado en Resúmenes de los Trabajos del VIII Congreso TAEE Universidad de Zaragoza Zaragoza, 2-4 Julio 2008Se propone una nueva orientación para la asignatura Sistemas Electrónicos Digitales donde se enseñe a los alumnos a modelar sistemas en VHDL partiendo de esquemas desarrollados en Matlab/Simulink para posteriormente abordar propuestas de controladores digitales sintetizables integrados en la descripción del sistema. De esta forma, la asignatura no sólo se dirige a alumnos de la intensificación sino que se puede incorporar a currículos multidisciplinares dentro de los estudios de ingeniería

Autotuning digital controller for current sensorless power factor corrector stage in continuous conduction mode

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. López, F. J. Azcondo, F. J. Díaz, and Á. de Castro, "Autotuning digital controller for current sensorless power factor corrector stage in continuous conduction mode", 2010 IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL), Boulder (CO), 2010, pp. 1-8A circuit that compensates the volt-seconds error across the inductor in current sensorless digital control for continuous conduction mode power factor correction (PFC) stage is presented. Low cost ad-hoc sigma-delta analog to digital converters (ΣΔ ADCs) are used to sample the PFC input and output voltage. Instead of being measured, the input current is estimated in a digital circuit to be used in the current loop. A nonlinear carrier control is implemented in the digital controller in order to obtain the power factor correction. Drive signal delays cause differences between the digital current and the real current, producing that volt-seconds error. The control algorithm is compensated taking into account the delays. The influence of a wrong compensation is presented. Experimental results show power factor values and harmonic content within the IEC 61000-3-2 Class C standard in different operation conditions. Furthermore, the use of this PFC stage for electronic ballasts to compensate the effect of the utility voltage fluctuation in HID lamps is also verified taking advantage of the digital device capabilities.This work is sponsored by the Spanish Ministry of Education and Science through the project CICYT-TEC 2008-0175

Two-phase resonant converter to drive high-power LED lamps

This paper presents the design and modeling of a two-phase resonant converter that drives a LED lamp with a high-frequency pulsed current free of instabilities and flicker efect, fulfilling the recommendations of the IEEE PAR 1789-2015, so that it enables visible light-based communication at a 10 kB/s bit rate. The dynamic study of the converter takes into consideration the efect of the reflected impedance of the output filter on the AC side. In order to evaluate the dynamic response of the converter, a Spice model is defined. A 120 W prototype intended for street lighting applications has been built to validate the analysis and modeling.This work has been sponsored by the Spanish Ministry of Science and Innovation and the EU through the projects CICYT-FEDER-TEC2014-52316-R: “Estimation and Optimal Control for Energy Conversion with Digital Devices, ECOTRENDD” and RTI2018-095138-B-C31: “Power Electronics for the Grid and Industry Applications”

Improved noise immunity for two-sample PLL applicable to single-phase PFCs

Synchronization in a single-phase Power Factor Correction (PFC) is deteriorated, among others, by the combination of the noise introduced by the grid voltage sensing, conducted EMI, the ADC resolution and the sampling frequency used. Low signal-to-noise ratios (SNR) reduce the performance of the Two-Sample (2S) Phase Locked Loop (PLL). This effect can be compensated by including a smoothing filter action without increasing the overall complexity significantly. The resulting 2S with smoothing (2SS) is evaluated and validated by simulation and experimentally over a Totem Pole PFC.This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-BC31 PEGIA - Power Electronics for the Grid and Industry Applications

Power source electronic ballast for electrodeless fluorescent lamps

This paper presents the design, control strategy and experimental results of a two-step, power factor correction stage (PFC) and resonant inverter (RI), electronic ballast proposal to supply 150 W electrodeless fluorescent lamps (EFL). The PFC acts as a controlled power source and provides mid and long-term stability to the system, while the stability of the current through the lamp is achieved with the RI. In addition, the power-mode control requires limitation of the output voltage. The dual operation mode of the PFC (voltage source mode and power source mode) enables an e cient soft resonant ignition and the implementation of simple dimming regulation.This work has been supported by the Spanish Ministry of Science and Innovation and the EU through the projects CICYT-FEDER-TEC2014-52316-R: “Estimation and Optimal Control for Energy Conversion with Digital Devices, ECOTRENDD” and RTI2018-095138-B-C31 PEGIA: “Power Electronics for the Grid and Industry Applications”

Pulsed current source with active control of the on-time current for LED lamp driver applications

This paper presents a simplified envelope model to study the dynamics of a phase-controlled resonant converter suitable to drive light emitting diode (LED) lamps. The approximate closed form of the transfer function is obtained from the proposed reduced-order model. The fast dynamics of the resonant converter allows us implementing a pulsed current source with active control of the on-time-current free of instabilities and flicker effect with a type II or integral-single-lead controller. A 120W prototype intended for street lighting applications has been built to validate the study.This work is sponsored by the Spanish Ministry of Science and the EU through the project CICYT-FEDER- TEC2011- 23612: “Power conversion with new digital control techniques and soft-saturation magnetic cores”

Alternating current welding using four quadrant switches

Welding metals such as aluminum and magnesium requires AC current. This work proposes a novel control strategy for a high-frequency rectifier built with four quadrant switches (4QSW) to transform high frequency AC current (125 kHz) into the welding arc bipolar current, controlled in amplitude, frequency and even DC offset. The rectifier is connected to the output of a resonant inverter to achieve positive and negative polarity discharges both voltage and current by operating in two quadrants, i.e. positive and negative. As long as the input power to the converter is supplied by a current source, the typical dead-time set to avoid short circuit conditions jeopardize the safe operation of the switches. A field-programmable gate array (FPGA) is selected to implement the digital control due to its high resolution for the purpose to adapt the 4QSW's drive signals without dead-time in the most accurate manner.This work was supported by FEDER and the Spanish Ministry of Science through the project CICYT-FEDER TEC2011-23612: “Power conversion with new digital control techniques and soft-saturation magnetic cores

Evaluation of quadrature signal generation methods with reduced computational resources for grid synchronization of single-phase power converters through phase-locked loops

Low-cost single-phase grid connected converters require synchronization with the grid voltage to obtain a better response and protection under diverse conditions, such as frequency perturbations and distortion. Phase-locked loops (PLLs) have been used in this scenario. This paper describes a set of quadrature signal generators for single-phase PLLs; compares the performances by means of simulation tests considering diverse operation conditions of the electrical grid; proposes strategies to reduce the computational burden, considering fixed-point digital implementations; and provides both descriptive and quantitative comparisons of the required mathematical operations and memory units for implementation of the analyzed single-phase PLLs.This work has been supported by the Spanish Ministry of Science and Innovation under Project RTI2018-095138-B-C31 PEGIA—Power Electronics for the Grid and Industry Applications

Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. Lopez-Martin, F. J. Azcondo, and A. de Castro, "Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode", 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL), Kyoto (Japan), 2012, pp. 1-8A universal digital PFC current-sensorless controller based on control of estimated current is presented. Parasitic elements cause a small difference between the measured input voltage and the voltage across the inductance in a boost converter, which must be taken into account to estimate the input current in a sensorless PFC digital controller. To compensate for the deviation caused by the parasitic elements, and so minimize the current estimation error, the article proposes a digital feedback control technique that cancels the time difference between DCM operation time of the real input current (TinDCM) and the estimated current (TrebDCM). Experimental results, obtained using a boost PFC converter under different conditions, are shown for verification purposes.This work was supported by the Spanish Ministry of Science TEC FEDER 2011-2361

High-resolution error compensation in continuous conduction mode power factor correction stage without current sensor

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. López-Martín, F. J. Azcondo, and Á. de Castro, "High-resolution error compensation in continuous conduction mode power factor correction stage without current sensor", in 2012 15th International Power Electronics and Motion Control Conference (EPE/PEMC), Novi Sad (Serbia), 2012.Continuous conduction mode power factor correction (PFC) without input current measurement is a step forward with respect to previously proposed PFC digital controllers. Inductance volt-second (vsL) measurement in each switching period enables the estimation of input current, but an accurate compensation of the small errors in the measured vsL is required. Otherwise, they are accumulated over a half-cycle line, leading to an appreciable current distortion. A vsL estimation is proposed, measuring the input (vin) and the the output voltage (vo). Discontinuous conduction mode (DCM) occurs near input line zero crossings, and is also detected by measuring MOSFET vds. This article analyzes the current estimation error caused by errors in the on-time estimation and voltage measurements, and proposes the minimization of vsL errors by cancelling the difference between estimated DCM (TDCMinereb) and real DCM (TDCMin) times with a signal (vdig), generated in the digital device. Therefore, the current estimation is calibrated using digital signals during the operation in DCM. Feedfoward coarse time error compensation is carried out with the measured delay of the drive signal, and then a fine compensation is achieved with a feedback loop that adjusts vdig. Experimental results are shown for a 1 kW boost PFC converter.This work was supported in part by the Spanish Ministry of Science TEC - FEDER 2011-2361