3,977 research outputs found

    Primes in arithmetic progressions and semidefinite programming

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    Assuming the generalized Riemann hypothesis, we give asymptotic bounds on the size of intervals that contain primes from a given arithmetic progression using the approach developed by Carneiro, Milinovich and Soundararajan [Comment. Math. Helv. 94, no. 3 (2019)]. For this we extend the Guinand-Weil explicit formula over all Dirichlet characters modulo q3q \geq 3, and we reduce the associated extremal problems to convex optimization problems that can be solved numerically via semidefinite programming.Comment: 11 pages, 5 ancillary file

    Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS

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    Actualmente, las tecnologías CMOS submicrónicas son básicas para el desarrollo de los modernos sistemas basados en computadores, cuyo uso simplifica enormemente nuestra vida diaria en una gran variedad de entornos, como el gobierno, comercio y banca electrónicos, y el transporte terrestre y aeroespacial. La continua reducción del tamaño de los transistores ha permitido reducir su consumo y aumentar su frecuencia de funcionamiento, obteniendo por ello un mayor rendimiento global. Sin embargo, estas mismas características que mejoran el rendimiento del sistema, afectan negativamente a su confiabilidad. El uso de transistores de tamaño reducido, bajo consumo y alta velocidad, está incrementando la diversidad de fallos que pueden afectar al sistema y su probabilidad de aparición. Por lo tanto, existe un gran interés en desarrollar nuevas y eficientes técnicas para evaluar la confiabilidad, en presencia de fallos, de sistemas fabricados mediante tecnologías submicrónicas. Este problema puede abordarse por medio de la introducción deliberada de fallos en el sistema, técnica conocida como inyección de fallos. En este contexto, la inyección basada en modelos resulta muy interesante, ya que permite evaluar la confiabilidad del sistema en las primeras etapas de su ciclo de desarrollo, reduciendo por tanto el coste asociado a la corrección de errores. Sin embargo, el tiempo de simulación de modelos grandes y complejos imposibilita su aplicación en un gran número de ocasiones. Esta tesis se centra en el uso de dispositivos lógicos programables de tipo FPGA (Field-Programmable Gate Arrays) para acelerar los experimentos de inyección de fallos basados en simulación por medio de su implementación en hardware reconfigurable. Para ello, se extiende la investigación existente en inyección de fallos basada en FPGA en dos direcciones distintas: i) se realiza un estudio de las tecnologías submicrónicas existentes para obtener un conjunto representativo de modelos de fallos transitoriosAndrés Martínez, DD. (2007). Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1943Palanci

    Economic evaluation of laparoscopic surgery for colorectal cancer

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    Objectives: To assess the cost-effectiveness of laparoscopic surgery compared with open surgery for the treatment of colorectal cancer. Methods: A Markov model was developed to model cost-effectiveness over 25 years. Data on the clinical effectiveness of laparoscopic and open surgery for colorectal cancer were obtained from a systematic review of the literature. Data on costs came from a systematic review of economic evaluations and from published sources. The outcomes of the model were presented as the incremental cost per life year gained and using cost-effectiveness acceptability curves (CEACs) to illustrate the likelihood that a treatment was cost-effective at various threshold values for society’s willingness to pay for an additional life year. Results: Laparoscopic surgery was on average £300 more costly and slightly less effective than open surgery and had a 30% chance of being cost-effective if society is willing to pay £30,000 for a life year. One interpretation of the available data suggests equal survival and disease-free survival. Making this assumption, laparoscopic surgery had a greater chance of being considered cost-effective. Presenting the results as incremental cost per quality adjusted life year (QALY) made no difference to the results, as utility data were poor. Evidence suggests short-term benefits following laparoscopic repair. This benefit would have to be at least 0.01 of a QALY for laparoscopic surgery to be considered cost-effective. Conclusions: Laparoscopic surgery is likely to be associated with short-term quality of life benefits, similar long-term outcomes and an additional £300 per patient. A judgement is required as to whether the short-term benefits are worth this extra cost.Peer reviewedAuthor versio

    El impacto de los conjuntos de trilleros en el registro paleolítico de la Meseta. Una aproximación etnoarqueológica

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    This paper analyzes the problem of the many archaeological assemblages found in the Castilian Meseta and created by the recent and contemporary activity of threshing cereals using wooden boards with stone tools (‘trillero’), which can be misinterpreted as of Palaeolithic age. The process of threshing using quartzite stones is systematically described, as well as the knapping technology used to make the cutting tools and the geological and archaeological formation of the assemblages.En el siguiente artículo se plantea la problemática que conlleva para el estudio del Paleolítico muchos depósitos líticos de carácter etnográfico y época histórica que se confunden con el registro arqueológico más antiguo. La principal aportación de este trabajo es la sistematización del proceso de elaboración de piedras de trillo en cuarcitas, y la caracterización geológica y arqueológica de estos conjuntos líticos en el territorio de Segovia

    Systematic review of economic evaluations of laparoscopic surgery for colorectal cancer

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    Objective Colorectal cancer is one of the most common cancers and the standard surgical treatment for this cancer is open resection (OS), but laparoscopic surgery (LS) may be an alternative treatment. In 2000, a Health Technology Assessment (HTA) review found little evidence on costs and cost-effectiveness in comparing the two methods. The evidence base has since expanded and this study systematically reviews the economic evaluations on the subject published since 2000. Method Systematic review of studies reporting costs and outcomes of LS vs OS for colorectal cancer. National Health Service Economic Evaluation Database (NHS EED) methods for abstract writing were followed. Studies were summarized and incremental cost-effectiveness ratios (ICER) for common outcomes were calculated. Results Five studies met the inclusion criteria. LS generally had higher healthcare costs. Most studies reported longer operational time and shorter length of stay and similar long-term outcomes with LS vs OS. Only one outcome, complications, was common across all studies but results lacked consistency (e.g. in two studies, OS was less costly but more effective; in another study, LS was less costly but more effective; and in the further two studies, LS could potentially be cost effective depending on the decision-makers' willingness to pay for the health gain). Conclusion The evidence on cost-effectiveness is not consistent. LS was generally more costly than OS. However, the effectiveness data used in individual economic evaluation were imprecise and unreliable when compared with data from systematic reviews of effectiveness. Nevertheless, short-term benefits of LS (e.g. shorter recovery) may make LS appear less costly when productivity gains are considered.Department of Health, National Coordinating Centre for Health Technology Assessment, Chief Scientist Office of the Scottish Government Health DirectoratesPeer reviewedAuthor versio

    An Application of Cooperative Game Theory to Distributed Control

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    18th World CongressThe International Federation of Automatic ControlMilano (Italy) August 28 - September 2, 2011In this paper we propose to study the underlying properties of a given distributed control scheme in which a set of agents switch between different communication strategies that define which network links are used in order to regulate to the origin a set of unconstrained linear systems. The problems of how to decide the time-varying communication strategy, share the benefits/costs and detect which are the most critical links in the network are solved using tools from game theory. The proposed scheme is demonstrated through a simulation example

    Los interlocking directorates en España: evolución, poder y consejeros independientes

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    Esta investigación explora la evolución de las redes sociales formadas por la conexión entre consejos de administración —relación interlocking directorates— de las empresas cotizadas españolas en el periodo 1999-2008, mostrándose como una nueva dimensión en el estudio del gobierno corporativo. Permite descubrir cómo se estructura el poder en la esfera económica, avanzar en la comprensión del papel desarrollado por el consejo de administración y ahondar en el rol de los consejeros independientes propiciados por los códigos de buen gobierno. Los resultados muestran cambios estructurales en la red, fragmentándose en mayor medida en los últimos años y con menores valores de densidad, características más propias de redes de países anglosajones. El análisis de centralidad evidencia un desplazamiento de las empresas del sector financiero a posiciones más periféricas, otorgando mayor protagonismo a empresas privadas del sector energético o de la construcción, intuyendo un cambio del modelo de banca a un modelo más anglosajón.Financiación recibida por parte del Ministerio de Educación, Cultura y Deporte a través del programa de Formación del Profesorado Universitario (FPU) y del Ministerio de Economía y Competitividad por el proyecto de investigación con referencia ECO2012-3255

    Cycling habits and other psychological variables affecting commuting by bicycle in city of Madrid

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    To develop effective cycling policies, decision makers and administrators should know the factors influencing the use of the bicycle for daily mobility. Traditional discrete choice models tend to be based on variables such as time and cost, which do not sufficiently explain the choice of the bicycle as a mode of transportation. Because psychological factors have been identified as particularly influential in the decision to commute by bicycle, this paper examines the perceptions of cycling factors and their influence on commuting by bicycle. Perceptions are measured by attitudes, other psychological variables, and habits. Statistical differences in the variables are established in relation to the choice of commuting mode and bicycle experience (commuter, sport–leisure, no use). Doing so enables the authors to identify the main barriers to commuting by bicycle and to make recommendations for cycling policies. Two underlying structures (factors) of the attitudinal variables are identified: direct benefits and long-term benefits. Three other factors are related to variables of difficulty: physical conditions, external facilities, and individual capacities. The effect of attitudes and other psychological variables on people’s decision to cycle to work–place of study is tested by using a logit model. In the case study of Madrid, Spain, the decision to cycle to work– place of study is heavily influenced by cycling habits (for noncommuting trips). Because bicycle commuting is not common, attitudes and other psychological variables play a less important role in the use of bikes

    Challenges of the market for initial coin offerings

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    This article analyzes the main problems and the solutions adopted in the market for Initial Coin Offerings (ICO), to anticipate the future of this market and determine implications for issuers, investors and regulators. ICOs represent an alternative and innovative financing solution that has experienced spectacular growth and notoriety in recent years. ICOs rely on Blockchain protocols and the ICO market is, therefore, characterized as decentralized, disintermediated and unregulated. Our results show that although the ICO market is innovative, it already displays many of the problems of traditional financial markets, and that these problems were at the genesis of the last financial crisis. Our analysis of the problems and solutions adopted shows a tension between what the Blockchain technology offers, and the problems associated with the financing of innovation. Considering the problems and solutions adopted, we no longer expect the ICO market to be characterized as disintermediated, unregulated or even decentralized in the near future. Furthermore, it is a real possibility that ICOs may end up being a progressor model eventually replaced by similar but more specialized financing models, some of which may already exist. With respect to the particular solutions of the ICO market, while some represent the realization of the potential of Blockchain, others such as forks have important Governance implications with the potential to create as many problems as the ones they addressWe acknowledge financial support from the Spanish Ministry of Economy and Competitiveness, Project PID2020-118064GB-I00 and from the Professorship Excellence Program in accordance with the multi-year agreement signed by the Government of Madrid and the Universidad Aut´onoma de Madrid (Line #3). R. Correia and A. Rezola acknowledge financial support from the Comunidad de Madrid Research Project for Young Researchers (SI3-PJI- 2021-00276). D. Arroyo acknowledges financial support from the Comunidad de Madrid (Spain) under the project CYNAMON (P2018/TCS-4566), and from the Spanish State Research Agency (AEI) of the Ministry of Science and Innovation (MCIN), project P2QProMeTe (PID2020-112586RBI00/ AEI/10.13039/501100011033), co-funded by the European Regional Development Fund (ERDF, EU

    Simulating the effects of logic faults in implementation-level VITAL-compliant models

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    [EN] Simulation-based fault injection is a well-known technique to assess the dependability of hardware designs specified using hardware description languages (HDL). Although logic faults are usually introduced in models defined at the register transfer level (RTL), most accurate results can be obtained by considering implementation-level ones, which reflect the actual structure and timing of the circuit. These models consist of a list of interconnected technology-specific components (macrocells), provided by vendors and annotated with post-place-and-route delays. Macrocells described in the very high speed integrated circuit HDL (VHDL) should also comply with the VHDL initiative towards application specific integrated circuit libraries (VITAL) standard to be interoperable across standard simulators. However, the rigid architecture imposed by VITAL makes that fault injection procedures applied at RTL cannot be used straightforwardly. This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models. The generality of this proposal is supported by the definition of a platform-specific fault procedure based on these operations. Three embedded processors, implemented using the Xilinx¿s toolchain and SIMPRIM library of macrocells, are considered as a case study, which exposes the gap existing between the robustness assessment at both RTL and implementation-level.This work has been partially funded by the Ministerio de Economia, Industria y Competitividad of Spain under grant agreement no TIN2016-81075-R, and the "Programa de Ayudas de Investigacion y Desarrollo" (PAID) of Universitat Politecnica de Valencia.Tuzov, I.; De-Andrés-Martínez, D.; Ruiz, JC. (2019). Simulating the effects of logic faults in implementation-level VITAL-compliant models. Computing. 101(2):77-96. https://doi.org/10.1007/s00607-018-0651-4S77961012Baraza JC, Gracia J, Blanc S, Gil D, Gil P (2008) Enhancement of fault injection techniques based on the modification of vhdl code. IEEE Tran Very Large Scale Integr Syst 16:693–706Baraza JC, Gracia J, Gil D, Gil P (2002) A prototype of a vhdl-based fault injection tool: description and application. Journal of Systems Architecture 47(10):847–867Benites LAC, Kastensmidt FL (2017) Fault injection methodology for single event effects on clock-gated asics. In: IEEE Latin American test symposium. IEEE, pp 1–4Benso A, Prinetto P (2003) Fault injection techniques and tools for VLSI reliability evaluation. Frontiers in electronic testing. Kluwer Academic Publishers, BerlinCobham Gaisler AB: LEON3 processor product sheet (2016). https://www.gaisler.com/doc/leon3_product_sheet.pdfCohen B (2012) VHDL coding styles and methodologies. Springer, New YorkDas SR, Mukherjee S, Petriu EM, Assaf MH, Sahinoglu M, Jone WB (2006) An improved fault simulation approach based on verilog with application to ISCAS benchmark circuits. In: IEEE instrumentation and measurement technology conference, pp 1902–1907Fernandez V, Sanchez P, Garcia M, Villar E (1994) Fault modeling and injection in VITAL descriptions. In: Third annual Atlantic test workshop, pp o1–o4Gil D, Gracia J, Baraza JC, Gil P (2003) Study, comparison and application of different vhdl-based fault injection techniques for the experimental validation of a fault-tolerant system. J Syst Archit 34(1):41–51Gil P, Arlat J, Madeira H, Crouzet Y, Jarboui T, Kanoun K, Marteau T, Duraes J, Vieira M, Gil D, Baraza JC, Gracia J (2002) Fault representativeness. Technical report, dependability benchmarking projectGuthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) MiBench: a free, commercially representative embedded benchmark suite. In: IEEE 4th annual workshop on workload characterization, pp 3–14IEEE Standard for VITAL ASIC (Application Specific Integrated Circuit) (2000) Modeling specification. Institute of Electrical and Electronic Engineers, StandardIEEE Standard VHDL Language Reference Manual (2008) Institute of Electrical and Electronic Engineers, StandardIEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process. Institute of Electrical and Electronic Engineers, Standard (2001)Jenn E, Arlat J, Rimen M, Ohlsson J, Karlsson J (1994) Fault injection into VHDL models: the MEFISTO tool. In: International symposium on fault-tolerant computing, pp 66–75Kochte MA, Schaal M, Wunderlich HJ, Zoellin CG (2010) Efficient fault simulation on many-core processors. In: Design automation conference, pp 380–385Mansour W, Velazco R (2013) An automated seu fault-injection method and tool for HDL-based designs. IEEE Trans Nucl Sci 60(4):2728–2733Mentor Graphics (2016) Questa SIM command reference manual 10.7b, Document Revision 3.5. https://www.mentor.com/products/fv/modelsim/Munden R (2000) Inverter, STDN library. Free model foundry VHDL model list. https://freemodelfoundry.com/fmf_models/stnd/std04.vhdMunden R (2004) ASIC and FPGA verification: a guide to component modeling. Systems on silicon. Elsevier, AmsterdamNa J, Lee D (2011) Simulated fault injection using simulator modification technique. ETRI J 33(1):50–59Nimara S, Amaricai A, Popa M (2015) Sub-threshold cmos circuits reliability assessment using simulated fault injection based on simulator commands. In: IEEE International Symposium on Applied Computational Intelligence and Informatics, pp 101–104Oregano Systems GmbH (2013) MC8051 IP Core, user guide (V 1.2) 2013. http://www.oreganosystems.at/download/mc8051_ug.pdfRomani E (1998) Structural PIC165X microcontroller. Hamburg VHDL archive. https://tams-www.informatik.uni-hamburg.de/vhdlShaw D, Al-Khalili D, Rozon C (2006) Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. Integr VLSI J 39(4):382–406Shaw DB, Al-Khalili D (2003) IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs. IEEE Trans Comput 10:1285–1297Short KL (2008) VHDL for engineers, 1st edn. Pearson, LondonSieh V, Tschache O, Balbach F (1997) Verify: evaluation of reliability using VHDL-models with embedded fault descriptions. In: International symposium on fault-tolerant computing, pp 32–36Singh L, Drucker L (2004) Advanced verification techniques. Frontiers in electronic testing. Springer, New YorkTuzov I, de Andrés D, Ruiz JC (2017) Dependability-aware design space exploration for optimal synthesis parameters tuning. In: IEEE/IFIP international conference on dependable systems and networks, pp 1–12Tuzov I, de Andrés D, Ruiz JC (2017) Robustness assessment via simulation-based fault injection of the implementation level models of the LEON3, MC8051, and PIC microcontrollers in presence of stuck-at, bit-flip, pulse, and delay fault models [Data set], Zenodo. https://doi.org/10.5281/zenodo.891316Tuzov I, de Andrés D, Ruiz JC (2018) DAVOS: EDA toolkit for dependability assessment, verification, optimization and selection of hardware models. In: IEEE/IFIP international conference on dependable systems and networks, pp 322–329Tuzov I, Ruiz JC, de Andrés D (2017) Accurately simulating the effects of faults in VHDL models described at the implementation-level. In: European dependable computing conference, pp 10–17Wang LT, Chang YW, Cheng KT (2009) Electronic design automation: synthesis, verification, and test. Morgan Kaufmann, BurlingtonXilinx: Synthesis and simulation design guide, UG626 (v14.4) (2012). https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sim.pd
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