A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Voltage drop tolerance by adaptive voltage scaling using clock-data compensation

Proyecto de Graduación (Maestría en Ingeniería en Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2019.El ruido de alta frecuencia en la red de alimentación compromete el rendimiento y la eficiencia energética de los sistemas electrónicos con microprocesadores, restringiendo la frecuencia máxima de operación de los sistemas y disminuyendo la confiabilidad de los dispositivos. La frecuencia máxima será determinada por la ruta de datos más crítica (la ruta de datos más lenta). De esta manera, es necesario configurar una banda de guarda para tolerar caídas de voltaje sin tener ningún problema de ejecución, pero sacrificando el rendimiento eléctrico. Este trabajo evalúa el impacto de la caída de voltaje en el rendimiento de los circuitos CMOS de alta densidad, estableciendo un conjunto de casos de prueba que contienen diferentes configuraciones de circuitos. Se desarrolló una técnica adaptable y escalable para mejorar la tolerancia a la caída de voltaje en los circuitos CMOS a través del escalado adaptativo, aprovechando el efecto de compensación de datos del reloj. La solución propuesta se validó aplicándola a diferentes casos de prueba en una tecnología FinFet-CMOS a nivel de simulación del diseño físico.High-frequency power supply noise compromises performance and energy efficiency of microprocessor-based products, restricting the maximum frequency of operation for electronic systems and decreasing device reliability. The maximum frequency is going to be determine by the most critical data path (the slowest data path). In this way, a guard band needs to be set in order to tolerate voltage drops without having any execution problem, but leading to a performance reduction. This work evaluates the impact of voltage drop in the performance of CMOS circuits by establishing a set of test cases containing different circuit configurations. An adaptive and scalable technique is proposed to enhance voltage drop tolerance in CMOS circuits through adaptive scaling, taking advantage of the clock-data compensation effect. The proposed solution is validated by applying it to different test cases in a FinFet CMOS technology at a post-layout simulation level

Robust low-power digital circuit design in nano-CMOS technologies

Device scaling has resulted in large scale integrated, high performance, low-power, and low cost systems. However the move towards sub-100 nm technology nodes has increased variability in device characteristics due to large process variations. Variability has severe implications on digital circuit design by causing timing uncertainties in combinational circuits, degrading yield and reliability of memory elements, and increasing power density due to slow scaling of supply voltage. Conventional design methods add large pessimistic safety margins to mitigate increased variability, however, they incur large power and performance loss as the combination of worst cases occurs very rarely. In-situ monitoring of timing failures provides an opportunity to dynamically tune safety margins in proportion to on-chip variability that can significantly minimize power and performance losses. We demonstrated by simulations two delay sensor designs to detect timing failures in advance that can be coupled with different compensation techniques such as voltage scaling, body biasing, or frequency scaling to avoid actual timing failures. Our simulation results using 45 nm and 32 nm technology BSIM4 models indicate significant reduction in total power consumption under temperature and statistical variations. Future work involves using dual sensing to avoid useless voltage scaling that incurs a speed loss. SRAM cache is the first victim of increased process variations that requires handcrafted design to meet area, power, and performance requirements. We have proposed novel 6 transistors (6T), 7 transistors (7T), and 8 transistors (8T)-SRAM cells that enable variability tolerant and low-power SRAM cache designs. Increased sense-amplifier offset voltage due to device mismatch arising from high variability increases delay and power consumption of SRAM design. We have proposed two novel design techniques to reduce offset voltage dependent delays providing a high speed low-power SRAM design. Increasing leakage currents in nano-CMOS technologies pose a major challenge to a low-power reliable design. We have investigated novel segmented supply voltage architecture to reduce leakage power of the SRAM caches since they occupy bulk of the total chip area and power. Future work involves developing leakage reduction methods for the combination logic designs including SRAM peripherals

GPU NTC Process Variation Compensation with Voltage Stacking

Near-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ˜80 % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ˜50 % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

메모리 어플리케이션을 위한 빠른 과도 응답 성능을 가지는 디지털 낮은 드롭아웃 레귤레이터 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.In this dissertation, the design of a fast transient response digital low-dropout regulator (DLDO) applicable to next-generation memory systems is discussed. Recent technologies in memory systems mainly aim at high power density and fast data rate. Accordingly, the need for a power converter withstanding a large amount of load current change in a short period is increased. Accordingly, a solution for compensating for a voltage drop that causes significant damage to a memory data input/output is searched according to a periodic clock signal. With this situation, two structures that achieve fast transient response performance under the constraints of memory systems are proposed. To mitigate the transient response degradation under slow external clock conditions, an adaptive two-step search algorithm with event-driven approaches DLDO is proposed. The technique solves the limitations of loop operation time dependent on slow external clocks through a ring-amplifier-based continuous-time comparator. Also, shift register is designed as a circular structure with centralized control of each register to reduce the cost. Finally, the remaining regulation error is controlled by an adaptive successive approximation algorithm to minimize the settling time. Fast recovery and settling time are shown through the measurement of the prototype chip implemented by the 40-nm CMOS process. Next, a digital low dropout regulator for ultra-fast transient response is designed. A slope-detector-based coarse controller to detect, compensate, and correct load current changes occurring at every rising or falling edge of tens to hundreds of megahertz clocks is proposed. Compensation efficiency is increased by the method according to the degree of change in load voltage over time. Furthermore, the LUT-based shift register enables the fast loop response speed of the DLDO. Finally, a bidirectional latch-based driver with fast settling speed and high resolution are proposed. The prototype chip is implemented with a 40-nm CMOS process and achieves effective load voltage recovery through fast transient response performance even with low load capacitance.본 논문은 차세대 메모리 시스템에 적용 가능한 빠른 과도 응답 성능을 가지는 디지탈 낮은 드롭아웃 레귤레이터의 설계에 대해 기술한다. 메모리 시스템의 최근 기술들은 높은 전력 밀도와 빠른 데이터 속도를 주된 목표로 하며 이에 맞추어 단기간, 많은 양의 부하 전류 변화를 견디는 파워 컨버터의 필요성이 높아지고 있다. 이에 주기적인 클락 신호에 따라 메모리 데이터 입출력에 유의미한 손상을 발생시키는 전압 강하를 보상하는 해결 방안을 탐색한다. 이를 통해 메모리 시스템이 가지는 제약조건 하에서 빠른 과도 응답 성능을 달성하는 두 가지 구조를 제안한다. 첫 번째 시연으로서, 느린 외부 클락 조건에서 유발되는 디지탈 낮은 드롭아웃 레귤레이터의 과도 응답 성능 저하를 완화시키기 위한 이벤트 주도 방식의 적응형 두 단계 서치 기술을 제안한다. 본 기술은 느린 외부클락에 의존한 루프 동작 시간의 한계를 고리 증폭기 기반 연속 시간 비교기를 통해 해결한다. 또한 자리 이동 레지스터의 구현에 소모되는 비용을 줄이고자 각 레지스터의 제어 장치를 중앙으로 집적시킨 순환형 구조로 설계되었다. 마지막으로 남아있는 조정 에러는 적응방식의 축차 비교형 알고리즘으로 제어하여 교정에 필요한 시간을 최소화하였다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 부하 전압의 빠른 회복 속도와 정정시간을 보임을 확인하였다. 두 번째 시연으로서, 초고속 과도 응답 환경에 적합한 디지털 낮은 드롭아웃 레귤레이터가 설계되었다. 수십~수백 메가헤르쯔 클락의 상승 또는 하강 엣지마다 발생하는 부하 전류 변화를 탐지하고 보상하고 정정하기 위해 기울기 탐지기 기반 coarse 제어기 기술을 제안한다. 시간에 따른 부하 전압 변화의 정도에 따라 차등 보상하는 알고리즘을 적용함으로써 보상 효율을 높였다. 나아가 순람표 기반 자리이동 레지스터는 부하 전류 과도 상태 이후 디지탈 레귤레이터의 빠른 루프 응답 속도를 가능케 하였다. 마지막으로 남은 조정 에러를 제어하는데 있어서 기존 자리이동 레지스터 방식에서 벗어나 빠른 수렴 속도와 높은 해상도를 가지는 양방향 래치 기반 드라이버가 제안되었다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 낮은 부하 축전용량에도 빠른 과도 응답 성능을 통해 효과적인 부하 전압 회복을 이루어 내었다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 VARIOUS TYPES OF LDO 4 1.2.1 ANALOG LDO VS. DIGITAL LDO 4 1.2.2 CAP LDO VS. CAP-LESS LDO 6 1.3 THESIS ORGANIZATION 8 CHAPTER 2 BACKGROUNDS ON DIGITAL LOW-DROPOUT REGULATOR 9 2.1 BASIC DIGITAL LOW-DROPOUT REGULATOR 9 2.2 FAST TRANSIENT RESPONSE LOW-DROPOUT REGULATOR 12 2.2.1 RESPONSE TIME 13 2.2.1 SETTLING TIME 20 2.3 VARIOUS METHODS FOR IMPLEMENT FAST TRANSIENT DIGITAL LDO 21 2.3.1 EVENT-DRIVEN DIGITAL LDO 21 2.3.2 FEEDFORWARD CONTROL 23 2.3.3 COMPUTATIONAL DIGITAL LDO 25 2.4 DESIGN POINTS OF FAST TRANSIENT RESPONSE DIGITAL LDO 27 CHAPTER 3 A FAST DROOP-RECOVERY EVENT-DRIVEN DIGITAL LDO WITH ADAPTIVE LINEAR/BINARY TWO-STEP SEARCH FOR VOLTAGE REGULATION IN ADVANCED MEMORY 29 3.1 OVERVIEW 29 3.2 PROPOSED DIGITAL LDO 32 3.2.1 MOTIVATION 32 3.2.2 ALSC WITH TWO-DIMENSIONAL CIRCULAR SHIFTING REGISTER 36 3.2.3 SBSC WITH SUBRANGE SUCCESSIVE-APPROXIMATION REGISTER 39 3.2.4 STABILITY ANALYSIS 41 3.3 CIRCUIT IMPLEMENTATION 44 3.3.1 TIME-INTERLEAVED RING-AMPLIFIER-BASED COMPARATOR 44 3.3.2 ASYNCHRONOUS 2D CIRCULAR SHIFTING REGISTER 49 3.3.3 SUBRANGE SUCCESSIVE APPROXIMATION REGISTER 51 3.4 MESUREMENT RESULTS 54 CHAPTER 4 A FAST TRANSIENT RESPONSE DIGITAL LOW-DROPOUT REGULATOR WITH SLOPE-DETECTOR-BASED MULTI-STEP CONTROL FOR DIGITAL LOAD APPLICATION 62 4.1 OVERVIEW 62 4.2 PROPOSED DIGITAL LDO 64 4.2.1 MOTIVATION 64 4.2.2 ARCHITECTURE OF DIGITAL LDO 66 4.2.3 SLEW-RATE DEPENDENT COARSE-CONTROL LOOP 69 4.2.4 FINE-CONTROL LOOP 72 4.2.5 CONTROL FOR LOAD-TRANSIENT RESPONSE 74 4.3 CIRCUIT IMPLEMENTATION 77 4.3.1 COMPARATOR-TRIGGERED OSCILLATOR DESIGN 77 4.3.2 SLOPE DETECTOR DESIGN 81 4.3.3 LUT-BASED SHIFT REGISTER DESIGN 84 4.3.4 BI-DIRECTIONAL LATCH-BASED DRIVER DESIGN 86 4.4 MEASUREMENT(SIMULATION) RESULTS 90 CHAPTER 5 CONCLUSION 95 BIBLIOGRAPHY 97 초 록 109박

Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device uncertainties, such as process, voltage, and temperature variations. To ensure system reliability, worst-case corner assumptions are usually made in each design level. However, the over-pessimistic worst-case margin leads to unnecessary power waste and performance loss as high as 2.2x. Since optimizations are traditionally confined to each specific level, those safe margins can hardly be properly exploited. To tackle the challenge, it is therefore advised in this Ph.D. thesis to perform a cross-layer optimization for digital signal processing circuits and systems, to achieve a global balance of power consumption and output quality. To conclude, the traditional over-pessimistic worst-case approach leads to huge power waste. In contrast, the adaptive voltage scaling approach saves power (25% for the CORDIC application) by providing a just-needed supply voltage. The power saving is maximized (46% for CORDIC) when a more aggressive voltage over-scaling scheme is applied. These sparsely occurred circuit errors produced by aggressive voltage over-scaling are mitigated by higher level error resilient designs. For functions like FFT and CORDIC, smart error mitigation schemes were proposed to enhance reliability (soft-errors and timing-errors, respectively). Applications like Massive MIMO systems are robust against lower level errors, thanks to the intrinsically redundant antennas. This property makes it applicable to embrace digital hardware that trades quality for power savings.Comment: 190 page

Monitor amb control strategies to reduce the impact of process variations in digital circuits

As CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous improvement of these devices in the near future. There are several ways to face the variability problem: to increase the operating margins of maximum clock frequency, the implementation of lithographic friendly layout styles, and the last one and the focus of this thesis, to adapt the circuit to its actual manufacturing and environment conditions by tuning some of the adjustable parameters once the circuit has been manufactured. The main challenge of this thesis is to develop a low-area variability compensation mechanism to automatically mitigate PVTA variations in run-time, i.e. while integrated circuit is running. This implies the development of a sensor to obtain the most accurate picture of variability, and the implementation of a control block to knob some of the electrical parameters of the circuit.A mesura que la tecnologia CMOS escala, les variacions de Procés, Voltatge, Temperatura i Envelliment (PVTA) tenen un impacte creixent en el rendiment i el consum de potència dels dispositius electrònics. Aquesta problemàtica podria arribar a frenar la millora contínua d'aquests dispositius en un futur proper. Hi ha diverses maneres d'afrontar el problema de la variabilitat: relaxar el marge de la freqüència màxima d'operació, implementar dissenys físics de xips més fàcils de litografiar, i per últim i com a tema principal d'aquesta tesi, adaptar el xip a les condicions de fabricació i d'entorn mitjançant la modificació d'algun dels seus paràmetres ajustables una vegada el circuit ja ha estat fabricat. El principal repte d'aquesta tesi és desenvolupar un mecanisme de compensació de variabilitat per tal de mitigar les variacions PVTA de manera automàtica en temps d'execució, és a dir, mentre el xip està funcionant. Això implica el desenvolupament d'un sensor capaç de mesurar la variabilitat de la manera més acurada possible, i la implementació d'un bloc de control que permeti l'ajust d'alguns dels paràmetres elèctrics dels circuits

Design tradeoffs and challenges in practical coherent optical transceiver implementations

This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.Fil: Morero, Damián Alfonso. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; ArgentinaFil: Castrillon, Alejandro. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; ArgentinaFil: Aguirre, Alejandro. ClariPhy Argentina S.A.; ArgentinaFil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; ArgentinaFil: Agazzi, Oscar Ernesto. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; Argentin