The MPI BUGS INITIATIVE: a Framework for MPI Verification Tools Evaluation

International audienceEnsuring the correctness of MPI programs becomes as challenging and important as achieving the best performance. Many tools have been proposed in the literature to detect incorrect usages of MPI in a given program. However, the limited set of code samples each tool provides and the lack of metadata stating the intent of each test make it difficult to assess the strengths and limitations of these tools. In this paper, we present the MPI BUGS INITIATIVE, a complete collection of MPI codes to assess the status of MPI verification tools. We introduce a classification of MPI errors and provide correct and incorrect codes covering many MPI features and our categorization of errors. The resulting suite comprises 1,668 codes, each coming with a well-formatted header that clarifies the intent of each code and specifies how to execute and evaluate it. We evaluated the completeness of the MPI BUGS INITIATIVE against eight stateof-the-art MPI verification tools

Static Analysis of a Concurrent Programming Language by Abstract Interpretation

Static analysis is an approach to determine information about the program without actually executing it. There has been much research in the static analysis of concurrent programs. However, very little academic research has been done on the formal analysis of message passing or process-oriented languages. We currently miss formal analysis tools and techniques for concurrent process-oriented languages such as Erasmus . In this dissertation, we focus on the problem of static analysis of large Erasmus programs. This can help us toward building more reliable Erasmus software systems. Reasoning about non-deterministic large Erasmus program using static analyzer is hard. These kinds of programs can quickly exhaust the computational and memory resources of the static analyzer tool. We use Abstract Interpretation to reason about Erasmus programs. To use the Abstract Interpretation theory, we introduce a lattice for Erasmus communications and an Event Order Predictor algorithm to statically determine the order that events happen in an Erasmus program. By using fixed-point theory of lattice, we compute a safe approximation of reachable states of an Erasmus programs. We also offer a Resettable Event order Vector for Erasmus processes to realistically implement our vector for large Erasmus programs using bounded space. We believe that our formal approach is also applicable to other types of process-oriented programs and MPI programs

An empirical evaluation of techniques for parallel simulation of message passing networks

209 p.[EN]In the field of computer design, simulation is an essential tool to validate and evaluate architectural proposals. Conventional simulation techniques, designed for their use in sequential computers, are too slow if the system to simulate is large or complex. The aim of this work is to search for techniques to accelerate simulations exploiting the parallelism available in current, commercial multicomputers, and to use these techniques to study a model of a message router. This router has been designed to constitute the communication infrastructure of a (hypothetical) massively parallel computer. Three parallel simulation techniques have been considered: synchronous, asynchronous-conservative and asynchronous-optimistic. These algorithms have been implemented in three multicomputers: a transputer-based Supernode, an Intel Paragon and a network of workstations. The influence that factors such as the characteristics of the simulated models, the organization of the simulators and the characteristics of the target multicomputers have in the performance of the simulations has been measured and characterized. It is concluded that optimistic parallel simulation techniques are not suitable for the considered kind of models, although they may provide good performance in other environments. A network of workstations is not the right platform for our experiments, because the communication demands of the parallel simulators surpass the abilities of local area networks—the granularity is too fine. Synchronous and conservative parallel simulation techniques perform very well in the Supernode and in the Paragon, specially if the model to simulate is complex or large—precisely the worst case for traditional, sequential simulators. This way, studies previously considered as unrealizable, due to their exceedingly high computational cost, can be performed in reasonable times. Additionally, the spectrum of possibilities of using multicomputers can be broadened to execute more than numeric applications.[ES]En el ámbito del diseño de computadores, la simulación es una herramienta imprescindible para la validación y evaluación de cualquier propuesta arquitectónica. Las ténicas convencionales de simulación, diseñadas para su utilización en computadores secuenciales, son demasiado lentas si el sistema a simular es grande o complejo. El objetivo de esta tesis es buscar técnicas para acelerar estas simulaciones, aprovechando el paralelismo disponible en multicomputadores comerciales, y usar esas técnicas para el estudio de un modelo de encaminador de mensajes. Este encaminador está diseñado para formar infraestructura de comunicaciones de un hipotético computador masivamente paralelo. En este trabajo se consideran tres técnicas de simulación paralela: síncrona, asíncrona-conservadora y asíncrona-optimista. Estos algoritmos se han implementado en tres multicomputadores: un Supernode basado en Transputers, un Intel Paragon y una red de estaciones de trabajo. Se caracteriza la influencia que tienen en las prestaciones de los simuladores aspectos tales como los parámetros del modelo simulado, la organización del simulador y las características del multicomputador utilizado. Se concluye que las técnicas de simulación paralela optimista no resultan adecuadas para trabajar con el modelo considerado, aunque pueden ofrecer un buen rendimiento en otros entornos. La red de estaciones de trabajo no resulta una plataforma apropiada para estas simulaciones, ya que una red local no reúne condiciones para la ejecución de aplicaciones paralelas de grano fino. Las técnicas de simulación paralela síncrona y conservadora dan muy buenos resultados en el Supernode y en el Paragon, especialmente si el modelo a simular es complejo o grande—precisamente el peor caso para los algoritmos secuenciales. De esta forma, estudios previamente considerados inviables, por ser demasiado costosos computacionalmente, pueden realizarse en tiempos razonables. Además, se amplía el espectro de posibilidades de los multicomputadores, utilizándolos para algo más que aplicaciones numéricas.Este trabajo ha sido parcialmente subvencionado por la Comisión Interministerial de Ciencia y Tecnología, bajo contrato TIC95-037

Unifying framework for development of message-passing applications

Import 19/05/2014This thesis focuses on the development of applications for distributed memory systems in the area of scientific and engineering computations. The work addresses the problems inherent to rapid development of parallel applications and the complexity of tools used during their implementation. Herein, an abstract computation model for describing MPI (Message Passing Interface) applications is proposed. In the described topic of interest, MPI is the de facto API. The proposed approach is based on the usage of visual programming for expressing parallel aspects and communication in a developed application. The intention is not to create a complete program visually; rather, a user writes sequential parts of the application in C++ and puts them into the visual program. This allows simple modification of the communication structure and provides immediate visual feedback of the program's behavior through a visual debugger. An abstract model is also designed in a way that provides a unified view of activities that are used during development, including debugging, performance analyses, and verifications. While tools exist in all of these areas, they are usually single-purpose tools. In the proposed approach, all these activities are roofed by a single conceptual frame; everything from configurations to providing results of analyses uses one set of terms. The thesis makes the following contributions: It introduces the syntax and semantics of the visual language for describing parallel aspects and communication in applications for distributed memory systems. The semantics of the language is formalized and the usage of the language is demonstrated for various problems. These examples show that the sizes of diagrams describing the visual programs remain reasonably small for many practical parallel applications. Measurements show that the performance of the resulting programs is close to manually created C++ applications. Also, the features of the proposed approach may help in various ways in common activities that occur during development. The ideas presented in this thesis are implemented as a tool named Kaira (\url{http://verif.cs.vsb.cz/kaira/}); it is an open source tool released under GPL (GNU General Public License).Tato práce se zabývá vývojem aplikací pro systémy s distribuovanou pamětí v oblasti vědecko-technických výpočtů. Práce se zaměřuje na rychlý vývoj para\-lelních aplikací a integraci nástrojů používaných při vývoji. Navržený přístup je založen na abstraktním výpočetním modelu a vizuálním programování. Tyto prostředky slouží k vyjádření paralelismu a komunikaci ve vyvíjené aplikaci. Sekvenční části aplikace jsou psány přímo v C++ a tento kód je kombinován s~vizuálním modelem. Navržený přístup dovoluje jednoduchou manipulaci s~programem a umožňuje poskytnout přímočarou vizualizaci chování aplikace. Abstraktní model je také navržen za účelem sjednocení aktivit, které se objevují při vývoji aplikací: debugování, analýza výkonu, predikce výkonu a verifikace. Pro tyto aktivity existuje mnoho různých etablovaných nástrojů, které jsou mnohem vyzrálejší a nabízejí více funkcí než zde předkládaná implementace. Z~pohledu této práce se ale většinou jedná o~programy zaměřené pouze na jednu z oblastí. Navrhovaný přístup spojuje všechny tyto aktivity do jednoho myšlenkového rámce s jednotnou terminologií, konfigurací a prezentací výsledků. Hlavní přínosy této práce spočívají ve vytvoření syntaxe a sémantiky vizuálního jazyka pro popis paralelních částí a komunikace v aplikacích pro systémy s distribuovanou pamětí. Sémantika jazyka je plně formalizována a využití jazyka je demonstrováno na různých příkladech. Tyto příklady ukazují, že diagramy reprezentující program zůstávají relativně malé a přehledné při řešení různých praktických problémů. V této práci je dále ukázáno, že navržený přístup může sjednotit a zjednodušit mnoho různých činností objevujících se v souvislosti s vývojem softwaru v oblasti zájmu této práce. Prezentované myšlenky jsou implementovány v podobě nástroje Kaira (\url{http://verif.cs.vsb.cz/kaira/}). Kaira je uvolněna jako open-source nástroj pod GPL (GNU General Public License).Prezenční460 - Katedra informatikyvyhově

A Domain Specific Language Based Approach for Generating Deadlock-Free Parallel Load Scheduling Protocols for Distributed Systems

In this dissertation, the concept of using domain specific language to develop errorree parallel asynchronous load scheduling protocols for distributed systems is studied. The motivation of this study is rooted in addressing the high cost of verifying parallel asynchronous load scheduling protocols. Asynchronous parallel applications are prone to subtle bugs such as deadlocks and race conditions due to the possibility of non-determinism. Due to this non-deterministic behavior, traditional testing methods are less effective at finding software faults. One approach that can eliminate these software bugs is to employ model checking techniques that can verify that non-determinism will not cause software faults in parallel programs. Unfortunately, model checking requires the development of a verification model of a program in a separate verification language which can be an error-prone procedure and may not properly represent the semantics of the original system. The model checking approach can provide true positive result if the semantics of an implementation code and a verification model is represented under a single framework such that the verification model closely represents the implementation and the automation of a verification process is natural. In this dissertation, a domain specific language based verification framework is developed to design parallel load scheduling protocols and automatically verify their behavioral properties through model checking. A specification language, LBDSL, is introduced that facilitates the development of parallel load scheduling protocols. The LBDSL verification framework uses model checking techniques to verify the asynchronous behavior of the protocol. It allows the same protocol specification to be used for verification and the code generation. The support to automatic verification during protocol development reduces the verification cost post development. The applicability of LBDSL verification framework is illustrated by performing case study on three different types of load scheduling protocols. The study shows that the LBDSL based verification approach removes the need of debugging for deadlocks and race bugs which has potential to significantly lower software development costs

Millipede: A graphical tool for debugging distributed systems with a multilevel approach

Much research and development has been applied to the problem of debugging computer programs. Unfortunately, most of this effort has been applied to solving the problem for traditional sequential programs with little attention paid to the parallel and distributed domains. Tracking down and fixing bugs in a parallel or distributed environment presents unique challenges for which these traditional sequential tools are simply not adequate. This thesis describes the development and usage of the Millipede debugging system, a graphical tool that applies the novel technique of multilevel debugging to the distributed debugging problem. By providing a user interface that offers the abstractions, flexibility, and granularity to handle the unique challenges that arise in this field, Millipede presents the user with an effective and compelling environment for the debugging of parallel and distributed programs, while avoiding many of the pitfalls encountered by its predecessors

Generalized Portable SHMEM library for high performance computing

The Generalized Portable SHMEM library (GPSHMEM) is a portable implementation of the SHMEM library originally released by Cray Research Inc. on the Cray T3D. SHMEM and GPSHMEM realize the distributed shared memory programming model, that is, a shared memory programming model in environments in which memory is physically distributed. It is intended for use on a large variety of hardware platforms, including distributed systems with a network interconnect. The programming interface of GPSHMEM follows that of SHMEM and includes remote memory access operations (one-sided communication) and a set of collective routines such as broadcast, collection and reduction. Programming interfaces for C and Fortran are provided. Because of the minimal assumptions about the underlying hardware, GPSHMEM does not implement the full SHMEM T3D interface. The lack of a few functions is compensated by a set of extensions, including dynamic memory allocation for Fortran 77. To ease porting of SHMEM-enabled scientific Fortran 77 code from the Cray machines to use with GPSHMEM, a specialized Fortran 77 preprocessor was designed and developed

Tools and Algorithms for the Construction and Analysis of Systems

This open access two-volume set constitutes the proceedings of the 27th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2021, which was held during March 27 – April 1, 2021, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2021. The conference was planned to take place in Luxembourg and changed to an online format due to the COVID-19 pandemic. The total of 41 full papers presented in the proceedings was carefully reviewed and selected from 141 submissions. The volume also contains 7 tool papers; 6 Tool Demo papers, 9 SV-Comp Competition Papers. The papers are organized in topical sections as follows: Part I: Game Theory; SMT Verification; Probabilities; Timed Systems; Neural Networks; Analysis of Network Communication. Part II: Verification Techniques (not SMT); Case Studies; Proof Generation/Validation; Tool Papers; Tool Demo Papers; SV-Comp Tool Competition Papers