Model order reduction of fully parameterized systems by recursive least square optimization

This paper presents an approach for the model order reduction of fully parameterized linear dynamic systems. In a fully parameterized system, not only the state matrices, but also can the input/output matrices be parameterized. The algorithm presented in this paper is based on neither conventional moment-matching nor balanced-truncation ideas. Instead, it uses “optimal (block) vectors” to construct the projection matrix, such that the system errors in the whole parameter space are minimized. This minimization problem is formulated as a recursive least square (RLS) optimization and then solved at a low cost. Our algorithm is tested by a set of multi-port multi-parameter cases with both intermediate and large parameter variations. The numerical results show that high accuracy is guaranteed, and that very compact models can be obtained for multi-parameter models due to the fact that the ROM size is independent of the number of parameters in our approach

Guaranteed passive parameterized model order reduction of the partial element equivalent circuit (PEEC) method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach

Parameterized model order reduction with guaranteed passivity for PEEC circuit analysis

We present a novel parameterized model order reduction technique applicable to the Partial Element Equivalent Circuit analysis that provides parametric reduced order models, stable and passive by construction, over a user defined design space. We treat the construction of parametric reduced order models on scattered design space grids. This new parameterized model order reduction technique is based on the hybridization of traditional passivity-preserving model order reduction methods and interpolation schemes based on a class of positive interpolation operators, in order to guarantee overall stability and passivity of the parametric reduced order model. Pertinent numerical examples validate the proposed approach

Passivity-preserving parameterized model order reduction for PEEC based full wave analysis

We present a novel parameterized model order reduction technique applicable to the Partial Element Equivalent Circuit method that is able to generate parametric reduced order models, stable and passive by construction, over a user defined design space. Overall stability and passivity of the parametric reduced order model are guaranteed by an efficient and reliable combination of traditional passivity-preserving model order reduction methods and interpolation schemes based on a class of positive interpolation operators. A pertinent numerical example validates the proposed parameterized model order reduction approach

Fast high-order variation-aware IC interconnect analysis

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, three practical interconnect delay and slew analysis methods are presented to facilitate efficient evaluation of wire performance variability. The first method is described in detail in Chapter III. It harnesses a collection of computationally efficient procedures and closed-form formulas. By doing so, process variations are directly mapped into the variability of the output delay and slew. This method can provide the closed-form formulas of the output delay and slew at any sink node of the interconnect nets fully parameterized, in-process variations. The second method is based on adjoint sensitivity analysis and driving point model. It constructs the driving point model of the driver which drives the interconnect net by using the adjoint sensitivity analysis method. Then the driving point model can be propagated through the interconnect network by using the first method to obtain the closedform formulas of the output delay and slew. The third method is the generalized second-order adjoint sensitivity analysis. We give the mathematical derivation of this method in Chapter V. The theoretical value of this method is it can not only handle this particular variational interconnect delay and slew analysis, but it also provides an avenue for automatical linear network analysis and optimization. The proposed methods not only provide statistical performance evaluations of the interconnect network under analysis but also produce delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. Experimental results show that superior accuracy can be achieved by our proposed methods

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Parameterized model order reduction for nonlinear dynamical systems

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 67-70).The presence of several nonlinear analog circuits and Micro-Electro-Mechanical (MEM) components in modern mixed signal System-on-Chips (SoC) makes the fully automatic synthesis and optimization of such systems an extremely challenging task. The research presented in this thesis concerns the development of techniques for generating Parameterized Reduced Order Models (PROMs) of nonlinear dynamical systems. Such reduced order models could serve as a first step towards the automatic and accurate characterization of geometrically complex components and subcircuits, eventually enabling their synthesis and optimization. This work combines elements from a non-parameterized trajectory piecewise linear method for nonlinear systems with a moment matching paramneterized technique for linear systems. Exploiting these two methods one can create four different algorithms or generating PROMs of nonlinear systems. The algorithms were tested on three different systems: a MEM switch and two nonlinear analog circuits. All three examples contain distributed strong nonlinearities and possess dependence on several geometric parameters.(cont.) Using the proposed algorithms, the local and global parameter-space accuracy of the reduced order models can be adjusted as desired. Models call be created which are extremely accurate over a narrow range of parameter values. as well as models which are less accurate locally but still provide adequate accuracy over a much wider range of parameter values.by Bradley N. Bond.S.M

Reduced-Order Equivalent-Circuit Models Of Thermal Systems Including Thermal Radiation

We established a general, automatic, and versatile procedure to derive an equivalent circuit for a thermal system using temperature data obtained from FE simulations. The EC topology was deduced from the FE mesh using a robust and general graph-partitioning algorithm. The method was shown to yield models that are independent of the boundary conditions for complicated 3D thermal systems such as an electronic chip. The results are strongly correlated with the geometry, and the EC can be extended to yield variable medium-order models. Moreover, a variety of heat sources and boundary conditions can be accommodated, and the EC models are inherently modular. A reliable method to compute thermal resistors connecting different regions was developed. It appropriately averages several estimates of a thermal resistance where each estimate is obtained using data obtained under different boundary or heating conditions. The concept of fictitious heat sources was used to increase the number of simulation datasets. The method was shown to yield models that are independent of the BCs for complicated 2-D thermal systems such as a 2D cavity. A reliable method to compute thermal resistors connecting different regions was developed. In general, the number of regions required for getting an accurate reduced-order model depends on the complexity of the system to be modeled. We have extended the reduced-order modeling procedure to include a view-factor based thermal radiation heat transfer model by including voltage controlled current sources in the equivalent circuit

Modeling and Analysis of Large-Scale On-Chip Interconnects

As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly critical and difficult. VLSI systems impacted by the increasingly high dimensional process-voltage-temperature (PVT) variations demand much more modeling and analysis efforts than ever before, while the analysis of large scale on-chip interconnects that requires solving tens of millions of unknowns imposes great challenges in computer aided design areas. This dissertation presents new methodologies for addressing the above two important challenging issues for large scale on-chip interconnect modeling and analysis: In the past, the standard statistical circuit modeling techniques usually employ principal component analysis (PCA) and its variants to reduce the parameter dimensionality. Although widely adopted, these techniques can be very limited since parameter dimension reduction is achieved by merely considering the statistical distributions of the controlling parameters but neglecting the important correspondence between these parameters and the circuit performances (responses) under modeling. This dissertation presents a variety of performance-oriented parameter dimension reduction methods that can lead to more than one order of magnitude parameter reduction for a variety of VLSI circuit modeling and analysis problems. The sheer size of present day power/ground distribution networks makes their analysis and verification tasks extremely runtime and memory inefficient, and at the same time, limits the extent to which these networks can be optimized. Given today?s commodity graphics processing units (GPUs) that can deliver more than 500 GFlops (Flops: floating point operations per second). computing power and 100GB/s memory bandwidth, which are more than 10X greater than offered by modern day general-purpose quad-core microprocessors, it is very desirable to convert the impressive GPU computing power to usable design automation tools for VLSI verification. In this dissertation, for the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with very promising performance. Our GPU based network analyzer is capable of solving tens of millions of power grid nodes in just a few seconds. Additionally, with the above GPU based simulation framework, more challenging three-dimensional full-chip thermal analysis can be solved in a much more efficient way than ever before