Analysis and Implementation of Median Type Filters

Median filters are a special class of ranked order filters used for smoothing signals. These filters have achieved- success in speech processing, image processing, and other impulsive noise environments where linear filters have proven inadequate. Although the implementation of a median filter requires only a simple digital operation, its properties are not easily analyzed. Even so, a number of properties have been exhibited in the literature. In this thesis, a new tool, known as threshold decomposition is introduced for the analysis and implementation of median type filters. This decomposition of multi-level signals into sets of binary signals has led to significant theoretical and practical breakthroughs in the area of median filters. A preliminary discussion on using the threshold decomposition as an algorithm for a fast and parallel VLSI Circuit implementation of ranked filters is also presented* In addition, the theory is developed both for determining the number of signals which are invariant to arbitrary window width median filters when any number of quantization levels are allowed and for counting or estimating the number of passes required to produce a root- i.e. invariant signal, for binary signals. Finally, the analog median filter is defined and proposed for analysis of the standard discrete median filter in cases with a large sample size or when the associated statistics would be simpler in the continuu

Ultra Low-Power Analog Median Filters

The design and implementation of three analog median filter topologies, whose transistors operate in the deep weak-inversion region, is described. The first topology is a differential pairs array, in which drain currents are driven into two nodes in a differential fashion, while the second topology is based on a wide range OTA, which is used to maximize the dynamic range. Finally, the third topology uses three range-extended OTAs. The proposed weak-inversion filters were designed and fabricated in ON Semiconductor 0.5 micrometer technology through MOSIS. Experimental results of three-input fabricated prototypes for all three topologies are show, where power consumptions of 90nW in the first case, and 270nW in the other two cases can be noticed. A dual power supply +/-1.5 Volts were used

Pruned Continuous Haar Transform of 2D Polygonal Patterns with Application to VLSI Layouts

We introduce an algorithm for the efficient computation of the continuous Haar transform of 2D patterns that can be described by polygons. These patterns are ubiquitous in VLSI processes where they are used to describe design and mask layouts. There, speed is of paramount importance due to the magnitude of the problems to be solved and hence very fast algorithms are needed. We show that by techniques borrowed from computational geometry we are not only able to compute the continuous Haar transform directly, but also to do it quickly. This is achieved by massively pruning the transform tree and thus dramatically decreasing the computational load when the number of vertices is small, as is the case for VLSI layouts. We call this new algorithm the pruned continuous Haar transform. We implement this algorithm and show that for patterns found in VLSI layouts the proposed algorithm was in the worst case as fast as its discrete counterpart and up to 12 times faster.Comment: 4 pages, 5 figures, 1 algorith

High throughput spatial convolution filters on FPGAs

Digital signal processing (DSP) on field- programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility

Hierarchical stack filtering : a bitplane-based algorithm for massively parallel processors

With the development of novel parallel architectures for image processing, the implementation of well-known image operators needs to be reformulated to take advantage of the so-called massive parallelism. In this work, we propose a general algorithm that implements a large class of nonlinear filters, called stack filters, with a 2D-array processor. The proposed method consists of decomposing an image into bitplanes with the bitwise decomposition, and then process every bitplane hierarchically. The filtered image is reconstructed by simply stacking the filtered bitplanes according to their order of significance. Owing to its hierarchical structure, our algorithm allows us to trade-off between image quality and processing time, and to significantly reduce the computation time of low-entropy images. Also, experimental tests show that the processing time of our method is substantially lower than that of classical methods when using large structuring elements. All these features are of interest to a variety of real-time applications based on morphological operations such as video segmentation and video enhancement

Design and implementation of a general purpose VLSI median filter unit and its applications

A VLSI median filter unit has been designed and implemented in 3-μ m M2 CMOS, using full-custom VLSI design techniques. The unit consists of two single-chip median filters, one extensible and one real-time. The chips are bit-level pipelined systolic structures based on odd/even transposition sorting. The extensible chip is designed for applications requiring variable window sizes and variable word-lengths, whereas the other one is for real-time applications. Various median filtering techniques are easily realized by using the designed chips together with reasonable external hardware

Single-clock-cycle two-dimensional median filter

Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block

General purpose VLSI median filter and its applications for image processing

A general-purpose median filter configuration consisting of two single-chip median filters is proposed. One of the chips is designed for applications requiring variable word-length and variable window size, whereas the other is for real-time applications. The architectures of the chips are based on odd/even transposition sorting. The chips are implemented in 3-μm M2CMOS using full-custom VLSI design techniques. The chips together with a reasonable external hardware can be used for the realizations of many median filtering techniques. The VLSI design procedure of the chips and their applications to different median filtering techniques for image processing are presented