Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block

Pedroni, V. A.

Yariv, A.

English

Caltech Authors - Main

4.. R 1  
‘-p--’ ‘--DyI 
Fig. 3 M F  realisatron 
p$ise or time delay used in common filter design. RCF fdters are 
mandatory for reducing IS1 in digital communication systems. The 
development of a novel active filter is presented in this Letter. The 
new filter, called the medium filter (MF), includes only two com- 
mon operational amplifier stages as shown in Fig. 3. The MF pro- 
vides significantly better IS1 performances than two- or even four- 
’ order BF as demonstrated in this Letter and shown in Table 1. 
0 IEE 1996 
Electronics Letters Online No: IY9&)319 
M. Bank and J. Gavan (Ccnter for  Technological Educutiorz Holon, 
POB 305, Holon 58/02, Isruel) 
M. Bank also with: The Hebrew University of Jerusalem. 91904, 
Jerusalem, Israel 
3 J a n u u q  1996 
References 
1 RODEN. M s : ‘Digital conmlunication systems design’ (Prentice-Hall. 
New Jersey, 1988) 
2 SCHWAKTZ. M : ‘Infroination transmission, modulation and noise’ 
(McGraw-Hill Publishing Co., 1990) 
3 GAVAN,  I : ‘Handbook of electromagnetic compatibility’ i7? PEREZ. R 
(Ed.): ‘Radio systems parameters and performance criteria 
concerning computation and mitigation of EM1 effects’ (Academic 
Press, 1995), Chap. 20 
4 BANK, M : ‘Analog integrated circuits of the radio apparatus’. 
Radio and Communication, Moscow, 1981 
5 JOHNSON, D., JOHMON. J . ,  and MOORE, H.: ‘A handbook of active 
filters‘ (Prentice-Hall, New Jersey, 1980) 
Single-clock-cycle two-dimensional median 
filter 
V.A. Pedroni and A. Yariv 
Indexing terms: Median Jlter.~, Filters, h u g e  processing 
Median filters are of interest to image processing due to their 
ability to remove impulsive noise. Conveiitional digital 
implementations of the median function, however, require 
multiple clock cycles, a number that is proportional to the sue of 
the 2-D data block. We present in the Letter a complete CMOS 
implementation, which consumes very little power and computes 
the median in just one clock cycle, independently from the size of 
the data block. 
Introduction: Median filters are of high interest in modem image 
processing applications due to their ability to remove impulsive 
noise without great edge disturbance [l,  21. They constitute a par- 
ticular case of rank filters in which the central element (the 
median) of the ordered set is to be selected. Performing the 
median function in a low time complexity fashion is a very chal- 
lenging exercise from the viewpoint of hardware implementation. 
Digital realisations of this function cannot be performed in a sin- 
gle clock cycle, even for one-dimensional data streams, regardless 
of the circuit architecture adopted. This fact is illustrated in Fig. 1, 
which shows a typical digital implementation of a median filter [l]. 
As can be seen, it relies on threshold decompositions of the M-val- 
ued components of the data block (of size N=n x n) into M ~ 1 
binary strings of length N,  which are then binarily filtered and 
later added together. In this kind of system (as in any digital 
median filter), it takes several clock cycles for the median element 
of the data set to be identified. Moreover, the number of clock 
cycles inevitably grows with the size of the data block. >I --. ,median - _ _  - - - -  filter; - 7’ 1 1  1 2 3 3 z2 
. - . - . - 
!threshold at 1,2anG31 [ binary adder I 
c3 0000 1 1 0 0 0  
000111 0 1 1  c3 0001 1 1  1 1  1 
110111 1 1 1  e 1 1 1 1 1  1 1 1 1  
binary 
median- filter 
Fig. 1 Conventional metiian jilter implementation example 
Single-clock-cycle 2 - 0  median Jilter circuit: We observe that, given 
a real-Yalued set X = {xl,  x2, ..., .xV}, the median of X can be com- 
puted as med(X) = min,{C,=,ilx, ~ ~ ~ 1 ) .  This equation indicates that 
an array of absolute-distance cells, when properly interconnected, 
can implement the median function directly and in a single clock 
cycle. Such a system is illustrated in Fig. 2. As shown in the inset, 
each individual cell has two inputs and two outputs. One output is 
equal (or linearly proportional) to the highest input, whereas the 
Fig. 2 2 - 0  nzediun filfer o j  O(1) time complexity 
a 
$ 
other is to the smallest one. Then, by applying a (digital) control 
signal HI/LO (higwlow), the outputs can be independently 
selected. While HI is active, the PRE @reset) signal is activated, 
prechai-gmg all rows with a reference voltage V,,,. After PRE is 
released, HI is disabled and LO is enabled. This causes the voltage 
of each row to be lowered proportionally to y, = C,=,NI~I ~ xJN,  j 
= 1; 2. _.., N (due to the action of the HVLO switch transistors 
and the coupling capacitors C). Therefore, the row that presents 
the smallest summation will stay closest to its initial level, V,,,. 
These row voltages are then applied directly to a winner-take-all 
(WTA) circuit (i.e. a circuit that detects the highest among its 
input voltages, e.g. [3, 41) The input signal to the row identified by 
the WTA is the median of the data set. Therefore, it takes only 
one clock cycle for the median to be computed in this implementa- 
tion. 
Fig. 3 depicts three absolute-distance cells. In (a) [5],  one side of 
the circuit is normally off, while the other is in subthreshold, being 
the central transistors needed in order to discharge the output 
nodes. In (b) [3],  on the other hand, the transistors operate in sat- 
uration. In both cases, a voltage-follower configuration is used, 
resulting in V,, - max {VI , V2 } and V,, - min{U;, V, 1, and 
similar performances. A more accurate cell is presented in (c), 
where a voltage comparator is employed to select the highest and 
lowest voltages directly; in this case, a higher transistor count also 
results. 
440 ELECTRONICS LETTERS 29th February 1996 Vol. 32 No. 5 
v1 E7 discharge node - '2 
References 
1' 1' 
a b 
Fig. 3 AIYsoluti4istance cell implementations 
Experimeniul results: A complete N=25 (5  x 5 )  system was fahri- 
cated using 1 . 2 ~  CMOS technology. The architecture adopted 
was that of Fig. 2, with distance cells of Fig. 3b [3] and the WTA 
circuit of [4]. The size of the chip was 1.6 x l.lmmz. The tests 
were realised with the 25 inputs separated into two blocks of 12 
elements each, plus a single element. The voltages Vin, and Vin2 
were applied to each of the two blocks, while Vmpd was applied to 
the single input. The results are depicted in Fig. 4. 
.......YW....Y......- .............. "l....... I ,...................... \ 
2 
2, 
I 
0 '. 
.A 
0 
a - 60 20 100 
(Vin, -Vin2)/2,rnV 
-10 30 50 70 110 
b Vmed - Vinl , mV 1619141 
Fig. 4 Experimental results 
+ median output, 0 other output 
V, = 3'V, VBIRs = 0.8V, V,,, = 2V, Vin, = 3.0V, Vinz = 3.1V 
In Fig. 4a, Vmed was kept fmed at 3V, while Vin, < Vmed and Vin, 
> yned were approximated gradually to Vmed (worst-case). As can 
be seen, the median was correctly identified when its value was 
-80mV or more from the other elements. In Fig. 4h, on the other 
hand, Vin, and Vin, were kept futed (at 3.0V and 3.1V, respec- 
tively, i.e., l00mV apart), while Vmed was varied. As can be seen, 
the median was correctly identified when it was -1OmV above the 
lower block voltage or 40mV below the higher. 
Conclusion: Computing the median function on 2-D pixel blocks 
with O( 1) time complexity is possible when the proper architecture 
is used. ;Such an architecture has been presented in this Letter, 
which makes use of ahsolute-distance cells and a WTA network. 
Experimental results, from an N=5 x 5 system, were also pre- 
sented. Accuracy in the 6-bit range is easily obtained in this kind 
of system, allowing therefore the computation on blocks of size > 
64 pixels. 
0 IEE 1996 
Electronics Letters Online No: 19960301 
V.A. Pedroni ( L A C  - Central R&D Laboratory, Centro Politecnico 
UFPR, CP 318, 80001-970 Curitiba, P R ,  Brazil) 
A. Yariv (California Institute of Technology, Electrical Engineering and 
Applied Physics, Pasadena, CA 91125, USA) 
2 January 1996 
ELECTRONICS LETTERS 29th February 1996 Vol. 32 
WENDT, P., COYLE, E., and GALLAGHER, s.: 'Stack filters', IEEE 
Trans. Acoust. Speech Signal Process., 1986, 34, pp. 898-91 1 
YLI-HARM, O., ASTOLA, J., and NEURO, Y.: 'Analysis Of the properties 
of median and weighted median filters using threshold logic and 
stack filter representation', IEEE Trans. Signal Process., 1991, 39, 
pp. 395410 
CAUWENBERGHS, G , and PEDRONI, v A.: 'A charge-based CMOS 
parallel analog vector quantizer'. Conference on Adv. Neural Inf. 
Process. Systems (NIPS), Denver, 1994 
PEDRONI, v A : 'Neural n-port voltage comparator network', 
Electron. Lett., 1994, 30, pp. 1114-1115 
PEDRONI, v.A.: 'VLSI systems for analog and Hamming parallel 
computation'. PhD thesis, California Institute of Technology, 1995 
Fractal coding Performance for first-order 
Gauss-Markov models 
B.E. Wohlberg  and G. de Jager 
Indexing terms: Fractals, Itnage coding 
Fixed block size fractal coding is evaluated for first-order Gauss- 
Markov models and the effects of varying tile correlation are 
presented. Performance for this class of statistical models is found 
to be significantly suboptimal. 
Introduction: In fractal coding [I] of signals (usually images), each 
signal is represented by the coefficients of a contractive affine 
transform on itself. The signal is tiled by nonoverlapping range 
blocks, and larger, possibly overlapping domain blocks. The glo- 
bal affine mapping consists of scaling and offset coefficients map- 
ping one of the domain blocks (after averaging to the range block 
width) to each range block. These coefficients are identified by use 
of the Collage theorem [2], which bounds the real error on decod- 
ing in terms of the collage error. While coding performance evalu- 
ations utilising test images have been promising [2], the 
performance of this coding method has not previously been evalu- 
ated for a statistical signal source, leaving fractal coding at a dis- 
advantage in comparison with traditional methods such as 
transform coding. 
Signal model: A Gaussian first-order Markov (or AR(1)) process 
X(n) is generated ([3], Chap. 2) by 
X ( n )  = Z ( n )  + p X ( n  - 1) 
where p is the correlation and Z(n) are independently distributed 
Gaussian values with variance 0;. The autocorrelation function of 
this process is R&) = o,'plk', with 0 2  = (1 ~ p')o:. Transform 
coding may be shown to be close to optimal for these models [3]. 
The performance of fixed block size fractal coding schemes for 
this model were investigated by calculating the distortion for each 
member of an ensemble of 1000 signals (restricted to 1-dimension 
to reduce computational requirements) randomly generated 
according to the model. Results are presented for signal size n, 
range block size r ,  domain block size 2r with the domain pool 
consisting of all domain blocks an increment of two samples 
apart, and contractivity bound s, (for all scaling .s, Is1 < s,,). All 
distortions are mean square error (MSE), with = 1 constant as 
p varies. 
Real and collage errors: Fig. 1 illustrates the difference between the 
collage and real error for signals of 4096 samples. In these and all 
other cases the real error was significantly greater than the collage 
error, with a decrease in the difference with increasing p. Since the 
collage error may be calculated more rapidly than the real error, it 
is used as a lower bound for the real error in many subsequent 
comparisons. 
Contractivity: Since s,, < 1 is sufficient, but not necessary, 
for contractivity [4], higher values are often employed. Fig. 2 
No. 5 44 1 


Single-clock-cycle two-dimensional median filter

Electronics Letters Online No:

PEDRONI, v A : 'Neural n-port voltage comparator network',

https://authors.library.caltech.edu/747/1/PEDel96.pdf

Single-clock-cycle two-dimensional median filter

Abstract

Similar works

Full text

Available Versions

Caltech Authors - Main