On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

Panoramic, large-screen, 3-D flight display system design

The report documents and summarizes the results of the required evaluations specified in the SOW and the design specifications for the selected display system hardware. Also included are the proposed development plan and schedule as well as the estimated rough order of magnitude (ROM) cost to design, fabricate, and demonstrate a flyable prototype research flight display system. The thrust of the effort was development of a complete understanding of the user/system requirements for a panoramic, collimated, 3-D flyable avionic display system and the translation of the requirements into an acceptable system design for fabrication and demonstration of a prototype display in the early 1997 time frame. Eleven display system design concepts were presented to NASA LaRC during the program, one of which was down-selected to a preferred display system concept. A set of preliminary display requirements was formulated. The state of the art in image source technology, 3-D methods, collimation methods, and interaction methods for a panoramic, 3-D flight display system were reviewed in depth and evaluated. Display technology improvements and risk reductions associated with maturity of the technologies for the preferred display system design concept were identified

Biological Networks

Networks of coordinated interactions among biological entities govern a myriad of biological functions that span a wide range of both length and time scales—from ecosystems to individual cells and from years to milliseconds. For these networks, the concept “the whole is greater than the sum of its parts” applies as a norm rather than an exception. Meanwhile, continued advances in molecular biology and high-throughput technology have enabled a broad and systematic interrogation of whole-cell networks, allowing the investigation of biological processes and functions at unprecedented breadth and resolution—even down to the single-cell level. The explosion of biological data, especially molecular-level intracellular data, necessitates new paradigms for unraveling the complexity of biological networks and for understanding how biological functions emerge from such networks. These paradigms introduce new challenges related to the analysis of networks in which quantitative approaches such as machine learning and mathematical modeling play an indispensable role. The Special Issue on “Biological Networks” showcases advances in the development and application of in silico network modeling and analysis of biological systems

Towards a practical implementation of coherent WDM:analytical, numerical, and experimental studies

Future optical networks will require the implementation of very high capacity (and therefore spectral efficient) technologies. Multi-carrier systems, such as Orthogonal Frequency Division Multiplexing (OFDM) and Coherent WDM (CoWDM), are promising candidates. In this paper, we present analytical, numerical, and experimental investigations of the impact of the relative phases between optical subcarriers of CoWDM systems, as well as the effect that the number of independently modulated subcarriers can have on the performance. We numerically demonstrate a five-subcarrier and three-subcarrier 10-GBd CoWDM system with direct detected amplitude shift keying (ASK) and differentially/coherently detected (D) phase shift keying (PSK). The simulation results are compared with experimental measurements of a 32-Gbit/s DPSK CoWDM system in two configurations. The first configuration was a practical 3-modulator array where all three subcarriers were independently modulated, the second configuration being a traditional 2-modulator odd/even configuration, where only odd and even subcarriers were independently modulated. Simulation and experimental results both indicate that the independent modulation implementation has a greater dependency on the relative phases between subcarriers, with a stronger penalty for the center subcarrier than the odd/even modulation scheme

Unraveling the regulation of mTORC2 using logical modeling

Background The mammalian target of rapamycin (mTOR) is a regulator of cell proliferation, cell growth and apoptosis working through two distinct complexes: mTORC1 and mTORC2. Although much is known about the activation and inactivation of mTORC1, the processes controlling mTORC2 remain poorly characterized. Experimental and modeling studies have attempted to explain the regulation of mTORC2 but have yielded several conflicting hypotheses. More specifically, the Phosphoinositide 3-kinase (PI3K) pathway was shown to be involved in this process, but the identity of the kinase interacting with and regulating mTORC2 remains to be determined (Cybulski and Hall, Trends Biochem Sci 34:620-7, 2009). Method We performed a literature search and identified 5 published hypotheses describing mTORC2 regulation. Based on these hypotheses, we built logical models, not only for each single hypothesis but also for all combinations and possible mechanisms among them. Based on data provided by the original studies, a systematic analysis of all models was performed. Results We were able to find models that account for experimental observations from every original study, but do not require all 5 hypotheses to be implemented. Surprisingly, all hypotheses were in agreement with all tested data gathered from the different studies and PI3K was identified as an essential regulator of mTORC2. Conclusion The results and additional data suggest that more than one regulator is necessary to explain the behavior of mTORC2. Finally, this study proposes a new experiment to validate mTORC1 as second essential regulator

Synthesis of Biological and Mathematical Methods for Gene Network Control

abstract: Synthetic biology is an emerging field which melds genetics, molecular biology, network theory, and mathematical systems to understand, build, and predict gene network behavior. As an engineering discipline, developing a mathematical understanding of the genetic circuits being studied is of fundamental importance. In this dissertation, mathematical concepts for understanding, predicting, and controlling gene transcriptional networks are presented and applied to two synthetic gene network contexts. First, this engineering approach is used to improve the function of the guide ribonucleic acid (gRNA)-targeted, dCas9-regulated transcriptional cascades through analysis and targeted modification of the RNA transcript. In so doing, a fluorescent guide RNA (fgRNA) is developed to more clearly observe gRNA dynamics and aid design. It is shown that through careful optimization, RNA Polymerase II (Pol II) driven gRNA transcripts can be strong enough to exhibit measurable cascading behavior, previously only shown in RNA Polymerase III (Pol III) circuits. Second, inherent gene expression noise is used to achieve precise fractional differentiation of a population. Mathematical methods are employed to predict and understand the observed behavior, and metrics for analyzing and quantifying similar differentiation kinetics are presented. Through careful mathematical analysis and simulation, coupled with experimental data, two methods for achieving ratio control are presented, with the optimal schema for any application being dependent on the noisiness of the system under study. Together, these studies push the boundaries of gene network control, with potential applications in stem cell differentiation, therapeutics, and bio-production.Dissertation/ThesisDoctoral Dissertation Biomedical Engineering 201

Silicon Photonics for All-Optical Processing and High-Bandwidth-Density Interconnects

Silicon photonics has emerged in recent years as one of the leading technologies poised to enable penetration of optical communications deeper and more intimately into computing systems than ever before. The integration potential of power efficient WDM links at the first level package or even deeper has been a strong driver for the rapid development this field has seen in recent years. The integration of photonic communication modules with very high bandwidth densities and virtually no bandwidth-distance limitations at the short reach regime of high performance computers and data centers has the potential to alleviate many of the bandwidth bottlenecks currently faced by board, rack, and facility levels. While networks on chip for chip multiprocessors (CMP) were initially deemed the target application of silicon photonic components, it has become evident in recent years that the initial lower hanging fruit is the CMP's I/O links to memory as well as other CMPs. The first chapter of the thesis provides more detailed motivation for the integration of silicon photonic modules into compute systems and surveys some of the recent developments in the field. The second chapter then proceeds to detail a technical case study of silicon photonic microring-based WDM links' scalability and power efficiency for these chip I/O applications which could be developed in the intermediate future. The analysis, initiated originally for a workshop on optical and electrical board and rack level interconnects, looks into a detailed model of the optical power budget for such a link capturing both single-channel aspects as well as WDM-operation-related considerations which are unique for a microring physical characteristics. The holistic analysis for the full link captures the wavelength-channel-spacing dependent characteristics, provides some methodologies for device design in the WDM-operation context, and provides performance predictions based on current best-of-class silicon photonic devices. The key results of the analysis are the determination of upper bounds on the aggregate achievable communication bandwidth per link, identifying design trade-offs for bandwidth versus power efficiency, and highlighting the need for continued technological improvements in both laser as well as photodetector technologies to allow acceptable power efficiency operation of such systems.The third chapter, while continuing on the theme silicon photonic high bandwidth density links, proceeds to detail the first experimental demonstration and characterization of an on-chip spatial division multiplexing (SDM) scheme based on microrings for the multiplexing and demultiplexing functionalities. In the context of more forward looking optical network-on-chip environments, SDM-enabled WDM photonic interconnects can potentially achieve superior bandwidth densities per waveguide compared to WDM-only photonic interconnects. The microring-based implementation allows dynamic tuning of the multiplexing and demultiplexing characteristic of the system which allows operation on WDM grid as well device tuning to combat intra-channel crosstalk. The characterization focuses on the first reported power penalty measurements for on-chip silicon photonic SDM link showing minimal penalties achievable with 3 spatial modes concurrently operating on a single waveguide with 10-Gb/s data carried by each mode. The chapter also details the first demonstration of WDM combined with SDM operation with six separate wavelength-and-spatial 10-Gb/s channels with error free operation and low power penalties. The fourth, fifth, and sixth chapters shift in topic from the application of silicon photonics to communication links to the evolving use of silicon waveguides for nonlinear all-optical processing. The unique tight mode confinement in sub-micron cross-sections combined with the high response of silicon have motivated the development of four-wave mixing (FWM)-based processing silicon devices. The key feature of the silicon platform for these nonlinear processing platforms is the ability to finely and uniformly control the dispersive properties of the optical structures in a way that enables completely offsetting the material dispersion and achieve dispersion profiles required for effective parametric interaction of waves in the optical structures. Chapter four primarily introduces and motivates nonlinear processing in communication applications and focuses on recent achievements in non-silicon and silicon FWM platforms. Chapter five describes some of the author's contributions on parametric processing of high speed data in silicon nonlinear devices, with first of a kind demonstrations of wavelength conversion of 160-Gb/s optically time division multiplexed (OTDM) data as well as the wavelength-multicasting of a 320-Gb/s OTDM stream. The chapter then details a methodical characterization and demonstration of several record wavelength conversion experiments of data in silicon with 40-Gb/s data wavelength-converted across more than 100 nm with only 1.4-dB of power penalties as well as the wavelength and format conversion of 10-Gb/s data across up to 168 nm with sensitivity gains stemming from the format conversion of about 2 dB and a residual conversion penalty of only 0.1 dB, achieved by implementing an improved experimental setup. Both experiments highlight the performance uniformity of the conversion process for a wide range of probe-idler detuning settings, showcasing the silicon platform's unique broadband phase matching properties. The sixth chapter presents a slight shift in motivation for parametric processing from traditional telecom-wavelength applications to functionalities developed targeting mid-IR operation. Parametric-processing in the silicon platform at long wavelengths holds large potential for performance improvements due to the elimination of two-photon absorption in silicon at long wavelengths as well as silicon's dispersion engineering capabilities which uniquely position the silicon platform for effective phase matching of significantly wavelength detuned waves. Four-wave mixing signal generation and reception at mid-IR wavelengths are attractive candidates for tunable flexible operation with modulation and detection speeds which are currently only available at telecom wavelengths. With this vision in mind, several contributions detailing extension of FWM functionalities in silicon to operate at wavelengths close to 2 μm with performance equivalent to much smaller detuning setting measurements. The contributions detail the experimental demonstration of the first silicon optical processing functionalities achieved at such long wavelengths including the wavelength conversion and unicast of 10-Gb/s signals with up to 700 nm of probe-idler detuning, the combined two-stage 10-Gb/s FWM-link in which both data generation and detection at 1900 nm is facilitated by parametric processing in silicon with only 2.1-dB overall penalty, the first ever 40-Gb/s receiver at 1900 nm based on a FWM stage for simultaneous temporal demultiplexing and wavelength conversion, and lastly, the demonstration of a 40-Gb/s FWM-link operation with only 3.6 dB of penalty. The chapter concludes with a short discussion on possible extensions to enable silicon parametric processing at even longer wavelengths targeting the mid-IR spectral transmission window of 3-5 μm

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd