Optimal Unknown Bit Filtering for Test Response Masking

[[abstract]]In this paper presents a new X-Masking scheme for response compaction. It filters all X states from test response that can no unknown value input to response compactor. In the experimental results, this scheme increased less control data and maintain same observability.[[conferencedate]]20121104~20121107[[iscallforpapers]]Y[[conferencelocation]]New Taipei, Taiwa

Stochastic Real-time Optimal Control: A Pseudospectral Approach for Bearing-Only Trajectory Optimization

A method is presented to couple and solve the optimal control and the optimal estimation problems simultaneously, allowing systems with bearing-only sensors to maneuver to obtain observability for relative navigation without unnecessarily detracting from a primary mission. A fundamentally new approach to trajectory optimization and the dual control problem is developed, constraining polynomial approximations of the Fisher Information Matrix to provide an information gradient and allow prescription of the level of future estimation certainty required for mission accomplishment. Disturbances, modeling deficiencies, and corrupted measurements are addressed with recursive updating of the target estimate with an Unscented Kalman Filter and the optimal path with Radau pseudospectral collocation methods and sequential quadratic programming. The basic real-time optimal control (RTOC) structure is investigated, specifically addressing limitations of current techniques in this area that lose error integration. The resulting guidance method can be applied to any bearing-only system, such as submarines using passive sonar, anti-radiation missiles, or small UAVs seeking to land on power lines for energy harvesting. Methods and tools required for implementation are developed, including variable calculation timing and tip-tail blending for potential discontinuities. Validation is accomplished with simulation and flight test, autonomously landing a quadrotor helicopter on a wire

Information Processing under Physiological Pulsatile Stimulation in a G-protein Coupled Signaling Pathway

The cellular microenvironment is often dynamic, and several physiological ligands are released in pulsatile bursts. The main hypothesis driving this study is that cells are able to discern these time-varying dynamic inputs and must have evolved to exploit the temporal information available in their microenvironment to their advantage. Taking Muscarinic M3 (a G-protein coupled receptor)-mediated signaling as an example, this thesis explores how information is processed under pulsatile stimulation. Several experimental and computational approaches techniques including microfluidics, real-time multi-color fluorescence imaging of single cells, reaction kinetics modeling and information and noise analysis are implemented to gain mechanistic insights into the signaling circuit architecture. A major finding of this thesis is that receptor-mediated signaling forms a low pass filter while downstream calcium-induced NFAT (Nuclear Factor of Activated T-Lymphocytes, a transcription factor) nuclear translocation forms a high pass filter. The combination acts as a band-pass filter optimized for intermediate frequencies of stimulation. Sensitivity analysis shows that receptor and downstream kinetics determine critical features of the band-pass and that the band-pass may be shifted for different receptors or NFAT dynamics. Another important finding in this thesis is that for weak physiological inputs, cells exhibit apparent stochastic responses that can be explained within a deterministic framework. Computational analysis suggests that cells may utilize apparent stochasticity to enhance selectivity in downstream responses. This thesis also demonstrates that pulsatile inputs enhance information transfer downstream in noisy biochemical pathways. Finally, a microfluidic experimental method is developed to measure two microfluidic observables in the same cell, similar to a ‘two-reporter’ system, to estimate biochemical noise. Analysis with this method suggests that effect of drug action increases with increasing biochemical noise. Although this thesis focuses on one particular receptor and ligand, the conclusions from this work may be applied to several signaling systems. Investigation of band-pass processing may lead to gaining mechanistic insights into hidden or unknown regulatory motifs in several signaling pathways that are poorly understood. Using pulsatility to modulate selectivity and sensitivity of signaling response amidst biochemical noise provides tools to synthetic biologists and pharmacologists for developing enhanced lab-on-chip devices and pharmaceutical interventions.PHDBiophysicsUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/135745/1/msumit_1.pd

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

Advanced Model Predictive Control Solutions for Performance Enhancement of Food Service Appliances

This work is done in collaboration with Prof. Felice Andrea Pellegrino and Prof. Gianfranco Fenu of the University of Trieste, my colleague Ph.D. Francesco Forte and my place of work in the AD\&T Laboratory at Electrolux Professional Group. The purpose of this research is the design of a control system with the aim of improving the performance of professional appliances dedicated to the food processing in order to meet the objectives of energy saving and culinary quality. Furthermore, it is necessary to design real-time control software that is able to predict the behavior of the device, estimate non-measurable physical quantities, respect the constraints on energy consumption imposed a priori, reduce the effect of delay response with the aim of having smarter and more robust solutions. Therefore, we apply the model predictive control (MPC) strategy in an industrial setting, specifically for controlling the temperature of Oven Professional Appliances. The workflow includes identifying and validating a model of the cell temperature and incorporating disturbance models. MPC is implemented using a state-space formulation. The proposed method shows significant energy saving and error tracking reduction with respect to the current oven control; its effectiveness has been demonstrated through several tests carried out on a professional oven.This work is done in collaboration with Prof. Felice Andrea Pellegrino and Prof. Gianfranco Fenu of the University of Trieste, my colleague Ph.D. Francesco Forte and my place of work in the AD\&T Laboratory at Electrolux Professional Group. The purpose of this research is the design of a control system with the aim of improving the performance of professional appliances dedicated to the food processing in order to meet the objectives of energy saving and culinary quality. Furthermore, it is necessary to design real-time control software that is able to predict the behavior of the device, estimate non-measurable physical quantities, respect the constraints on energy consumption imposed a priori, reduce the effect of delay response with the aim of having smarter and more robust solutions. Therefore, we apply the model predictive control (MPC) strategy in an industrial setting, specifically for controlling the temperature of Oven Professional Appliances. The workflow includes identifying and validating a model of the cell temperature and incorporating disturbance models. MPC is implemented using a state-space formulation. The proposed method shows significant energy saving and error tracking reduction with respect to the current oven control; its effectiveness has been demonstrated through several tests carried out on a professional oven

A Hardware Security Solution against Scan-Based Attacks

Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

TrustFed: A Reliable Federated Learning Framework with Malicious-Attack Resistance

As a key technology in 6G research, federated learning (FL) enables collaborative learning among multiple clients while ensuring individual data privacy. However, malicious attackers among the participating clients can intentionally tamper with the training data or the trained model, compromising the accuracy and trustworthiness of the system. To address this issue, in this paper, we propose a hierarchical audit-based FL (HiAudit-FL) framework, with the aim to enhance the reliability and security of the learning process. The hierarchical audit process includes two stages, namely model-audit and parameter-audit. In the model-audit stage, a low-overhead audit method is employed to identify suspicious clients. Subsequently, in the parameter-audit stage, a resource-consuming method is used to detect all malicious clients with higher accuracy among the suspicious ones. Specifically, we execute the model audit method among partial clients for multiple rounds, which is modeled as a partial observation Markov decision process (POMDP) with the aim to enhance the robustness and accountability of the decision-making in complex and uncertain environments. Meanwhile, we formulate the problem of identifying malicious attackers through a multi-round audit as an active sequential hypothesis testing problem and leverage a diffusion model-based AI-Enabled audit selection strategy (ASS) to decide which clients should be audited in each round. To accomplish efficient and effective audit selection, we design a DRL-ASS algorithm by incorporating the ASS in a deep reinforcement learning (DRL) framework. Our simulation results demonstrate that HiAudit-FL can effectively identify and handle potential malicious users accurately, with small system overhead.Comment: 13 pages, 9figure

Contract renewal as an incentive device. An application to the French urban public transport sector

In the French urban public transport industry, services are often delegated to a private firm by the mean of a fixed-term regulatory contract. This contract specifies the duties of the firm and a financial compensation. When it expires, a new contract is awarded, possibly to a different operator. Cost-plus and fixed-price (gross cost or net cost) contracts are commonly used to regulate the operators in the transport industry. In this paper, we analyse the incentives for the operator to reduce its cost. These incentives come from both the profit maximization during the current contract and the perspective of contract renewal. In our model, the amount of cost-reducing effort depends on the contract type and the time remaining till contract expiration. We use a sample of 124 French urban public transport networks covering the period 1995-2002 to test our predictions. Our proxy for the cost reducing effort is technical efficiency. The data largely confirm the importance of contract type on performances and the incentive effect of contract renewal.incentive regulation, urban transport, stochastic frontier analysis.

Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software ( C code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs