From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail

Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

DESIGN AND MICROFABRICATION OF A CMOS-MEMS PIEZORESISTIVE ACCELEROMETER AND A NANO-NEWTON FORCE SENSOR

DESIGN AND MICROFABRICATION OF A CMOS-MEMS PIEZORESISTIVE ACCELEROMETER AND A NANO-NEWTON FORCE SENSOR by Mohd Haris Md Khir Adviser: Hongwei Qu, Ph.D. This thesis work consists of three aspects of research efforts: I. Design, fabrication, and characterization of a CMOS-MEMS piezoresistive accelerometer 2. Design, fabrication, and characterization of a CMOS-MEMS nano-Newton force sensor 3. Observer-based controller design of a nano-Newton force sensor actuator system A low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass has been fabricated. Inherent CMOS polysilicon thin film was utilized as piezoresistive material and full Wheatstone bridge was constructed through easy wiring allowed by three metal layers in CMOS thin films. The device fabrication process consists of a standard CMOS process for sensor configuration and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. Bulk single-crystal silicon (SCS) substrate was included in the proof mass to increase sensor sensitivity. Using a low operating power of 1.67 m W, the sensitivity was measured as 30.7 mV/g after amplification and 0.077 mV/g prior to amplification. With a total noise floor of 1.03 mg!-!Hz, the minimum detectable acceleration is found to be 32.0 mg for a bandwidth of I kHz which is sufficient for many applications. The second device investigated in this thesis work is a CMOS-MEMS capacitive force sensor capable ofnano-Newton out-of-plane force measurement. Sidewall and fringe capacitance formed by the multiple CMOS metal layers were utilized and fully differential sensing was enabled by common-centroid wiring of the sensing capacitors. Single-crystal silicon (SCS) is incorporated in the entire sensing element for robust structures and reliable sensor deployment in force measurement. A sensitivity of 8 m V /g prior to amplification was observed. With a total noise floor of 0.63 mg!-IHz, the minimum detection acceleration is found to be 19.8 mg, which is equivalent to a sensing force of 449 nN. This work also addresses the design and simulation of an observer-based nonlinear controller employed in a CMOS-MEMS nano-Newton force sensor actuator system. Measurement errors occur when there are in-plane movements of the probe tip; these errors can be controlled by the actuators incorporated within the sensor. Observerbased controller is necessitated in real-world control applications where not all the state variables are accessible for on-line measurements. V

RS-485 Bus Design of a Missile Simulation Training System

In a missile simulation training system with one-master and multi-slaves distributed system structure, a universal controller is necessary due to the system composed with several controllers. In this research, the designed controllers communicate with each other and upper control computer through RS-485 field bus. RS-485 bus including interface circuits, transmission protocol, Cyclic Redundancy Check (CRC) method and upper control test software is designed and proposed. The universal controller adopting the designed RS-485 interface circuits is connected through twisted-pair and makes the simulation system, then the controller is tested in line. The results show that the RS-485 bus communicates effectively using the protocol and CRC method, data transmission rates reaches 115.2 kbps, and has a good stability

RS-485 Bus Design of a Missile Simulation Training System

In a missile simulation training system with one-master and multi-slaves distributed system structure, a universal controller is necessary due to the system composed with several controllers. In this research, the designed controllers communicate with each other and upper control computer through RS-485 field bus. RS-485 bus including interface circuits, transmission protocol, Cyclic Redundancy Check (CRC) method and upper control test software is designed and proposed. The universal controller adopting the designed RS-485 interface circuits is connected through twisted-pair and makes the simulation system, then the controller is tested in line. The results show that the RS-485 bus communicates effectively using the protocol and CRC method, data transmission rates reaches 115.2 kbps, and has a good stability