Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

Millimeter-Wave CMOS Digitally Controlled Oscillators for Automotive Radars

All-Digital-Phase-Locked-Loops (ADPLLs) are ideal for integrated circuit implementations and effectively generate frequency chirps for Frequency-Modulated-Continuous-Wave (FMCW) radar. This dissertation discusses the design requirements for integrated ADPLL, which is used as chirp synthesizer for FMCW automotive radar and focuses on an analysis of the ADPLL performance based on the Digitally-Controlled-Oscillator (DCO) design parameters and the ADPLL configuration. The fundamental principles of the FMCW radar are reviewed and the importance of linear DCO for reliable operation of the synthesizer is discussed. A novel DCO, which achieves linear frequency tuning steps is designed by arranging the available minimum Metal-Oxide-Metal (MoM) capacitor in unique confconfigurations. The DCO prototype fabricated in 65 nm CMOS fullls the requirements of the 77 GHz automotive radar. The resultant linear DCO characterization can effectively drive a chirp generation system in complete FMCW automotive radar synthesizer

Innovative Design and Realization of Microwave and Millimeter-Wave Integrated circuits

Ph.DDOCTOR OF PHILOSOPH

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Receptor super-regenerativo de baixo consumo para redes corporais

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2014.O foco deste trabalho é a análise e o projeto de um receptor super-regenerativo voltado para aplicações biomédicas. Primeiramente, apresenta-se a fundamentação teórica da recepção super-regenerativa e, em seguida, mostra-se um circuito projetado segundo essa arquitetura, a qual incorpora um amplificador de baixo ruído, um oscilador e um detector de envoltória, além de um conversor balanceado-desbalanceado entre estes dois últimos. O projeto demonstra a vantagem dessa técnica para projetar receptores de baixa potência e elevada sensibilidade. Como o oscilador tende a ser o circuito com maior consumo elétrico em um receptor super-regenerativo, esta dissertação também apresenta uma técnica de projeto de osciladores para aplicações de baixa potência. O circuito é baseado no clássico oscilador Colpitts de porta comum com uma segunda fonte de realimentação positiva, a qual é fornecida por uma degeneração indutiva de porta. Esta técnica diminui a transcondutância requerida para originar as oscilações, o que faz com que seja possível reduzir a corrente de polarização e, consequentemente, o consumo de potência. Um protótipo foi produzido em uma tecnologia CMOS padrão de 0,18 µm para servir de prova de conceito. Simulações pós-leiaute demonstraram uma frequência de oscilação de 2,5 GHz com um ruído de fase de -112.9 dBc/Hz a uma frequência deslocada de 1 MHz da portadora, consumindo 124 µW a partir de uma tensão de alimentação de 0,575 V.Abstract : The goal of this work is the analysis and the design of a super-regenerative receiver aimed for biomedical applications. Firstly the theoretical foundation of the super-regenerative reception is presented and afterwards it is shown a circuit designed according such an architecture, which incorporates a lownoise amplifier, an oscillator, and an envelope detector, besides a balancedto- unbalanced converter between the last two. This project demonstrates the advantage of that technique to design low-power and high-sensitivity receivers. Since the oscillator tends to be the circuit with the highest power consumption in a super-regenerative receiver, this dissertation also presents an oscillator design technique for low-power applications. The circuit is based on the common-gate Colpitts oscillator with additional positive feedback provided by an inductive gate degeneration. This technique decreases the required transconductance to start-up oscillations, which makes possible to reduce the bias current and hence the power consumption. A prototype was designed in a standard 0.18 mm CMOS technology as a proof of concept. Post-layout simulations present an oscillating frequency of 2.5 GHz with a phase noise of -112.9 dBc/Hz at a 1 MHz offset frequency and consuming 124 mW from a 0.575-V supply voltage

Ultra-low power RF receiver based on double-gate CMOS FinFET technology

In this research, design approaches and methodologies were presented to realize the ultra-low power RF receiver front-end circuits. Moderate inversion operation was explored as a possible method of reducing power consumption along with the use of low supply voltage. The research is firstly concentrated on passive and active devices modeling. One of the most commonly used passive devices is on-chip inductor. On-chip spiral inductor model was developed firstly. Compared to the model developed by others, this model can predict the behavior of the inductors with different structural parameters over a board frequency range (from 0.1 to 10 GHz). Then the SOI varactor model was developed based on our measurement and extraction.Besides the passive devices modeling, a new most promising MOSFET candidate, FinFET, was characterized at GHz frequency range. Based on the measurement results, we found the FinFET transistors did have superior performance over bulk-Si CMOS technology. And an RF circuit model of FinFET was developed followed that, which was published in Electronics Letters. To my best knowledge, this was the first RF FinFET model published world wide at that time. It provides the basic idea about how to model this new structure MOSFET.Based on the passive and active device models developed, Global Positioning System (GPS) receiver front end circuits were designed and measured. Comparing to the previous designs with the same constrains, the ultra-low power GPS receiver building block circuits in this research have much less power consumption than the best design published before

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO