New Techniques for Multi-Channel Biosignal Acquisition and Low-Power, Low-Resistance-Measurement Systems

Dense electrical recording of biosignals has been developed to provide spatial resolution and precise temporal information for health monitoring, diagnostics, and clinical research. However, more electrodes require more wires, and wiring density quickly becomes a limiting factor. To break this bottleneck, we proposed a frequency-division multiplexing (FDM) based architecture for multi-channel acquisition systems. In this final exam, I present two applications that make use of this FDM technique. The first is an FDM-based multi-channel electromyography (EMG) acquisition system, which demonstrates that the FDM system not only reduces wire count, but also mitigates the effect of low frequency motion artifacts and 50/60 Hz mains interference introduced in the wire. An FDM-based four-channel EMG recording is demonstrated, while carrying all channels over a 3-wire interface, and the system achieves an attenuation of low-frequency cable motion artifacts by 15X an! d 60Hz mains noise coupled in the cable by 62X. A second application that forms the basis of my current research effort is an FDM-based neural recording system with multiple graphene active electrodes. We demonstrated a two-channel system including graphene FET electrodes, a custom integrated circuit (IC) analog front-end (AFE), and digital demodulation. In related multi-channel sensor work, a growing need for ultra-low-power sensors has driven continuous advancement in read-out circuits for temperature, humidity, and pressure. IC-integrated Wheatstone bridges, commonly used, are efficient for large sensor resistance (5k-500kohm), but measuring small resistance (30,000x smaller nominal sensor resistance

Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach

This work proposes a Double Differential (DD) amplifier topology which exploits the advantages of the current-mode approach. DD amplifiers are useful as front-ends in standalone active electrodes for superficial electromyography (sEMG) wearable applications and electroneurography (ENG) measurement devices. Front-ends for these applications need to attain low noise, high common-mode rejection ratio, and high input impedance to measure biopotential signals and can further benefit from low power operation, a small size, and an easily adaptable output. Presently published DD amplifiers are either complex in terms of a high part count, leading to higher power consumption and size, or suffer from limited interference-rejection capabilities and require further analog processing for compatibility with single-ended systems. Therefore, in this work, second-generation current conveyors have been leveraged to obtain a simple topology combining a small active-part count, a high common-mode rejection ratio, and a flexible output stage. The current-mode DD amplifier is presented and analyzed in detail to estimate its parameters and model the effects of nonidealities in the circuit. In order to validate the proposed topology, a discrete-component implementation was realized as a proof-of-concept. The results experimentally demonstrated the properties of the proposed topology and its feasibility for measuring superficial sEMG DD signals.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señale

Ultra low power wearable sleep diagnostic systems

Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life. To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture. A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.Open Acces

A Low Power Low Noise Instrumentation Amplifier For ECG Recording Applications

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

Wearable electroencephalography for long-term monitoring and diagnostic purposes

Truly Wearable EEG (WEEG) can be considered as the future of ambulatory EEG units, which are the current standard for long-term EEG monitoring. Replacing these short lifetime, bulky units with long-lasting, miniature and wearable devices that can be easily worn by patients will result in more EEG data being collected for extended monitoring periods. This thesis presents three new fabricated systems, in the form of Application Specific Integrated Circuits (ASICs), to aid the diagnosis of epilepsy and sleep disorders by detecting specific clinically important EEG events on the sensor node, while discarding background activity. The power consumption of the WEEG monitoring device incorporating these systems can be reduced since the transmitter, which is the dominating element in terms of power consumption, will only become active based on the output of these systems. Candidate interictal activity is identified by the developed analog-based interictal spike selection system-on-chip (SoC), using an approximation of the Continuous Wavelet Transform (CWT), as a bandpass filter, and thresholding. The spike selection SoC is fabricated in a 0.35 μm CMOS process and consumes 950 nW. Experimental results reveal that the SoC is able to identify 87% of interictal spikes correctly while only transmitting 45% of the data. Sections of EEG data containing likely ictal activity are detected by an analog seizure selection SoC using the low complexity line length feature. This SoC is fabricated in a 0.18 μm CMOS technology and consumes 1.14 μW. Based on experimental results, the fabricated SoC is able to correctly detect 83% of seizure episodes while transmitting 52% of the overall EEG data. A single-channel analog-based sleep spindle detection SoC is developed to aid the diagnosis of sleep disorders by detecting sleep spindles, which are characteristic events of sleep. The system identifies spindle events by monitoring abrupt changes in the input EEG. An approximation of the median frequency calculation, incorporated as part of the system, allows for non-spindle activity incorrectly identified by the system as sleep spindles to be discarded. The sleep spindle detection SoC is fabricated in a 0.18 μm CMOS technology, consuming only 515 nW. The SoC achieves a sensitivity and specificity of 71.5% and 98% respectively.Open Acces

ULTRA LOW POWER CIRCUITS FOR WEARABLE BIOMEDICAL SENSORS

Ph.DDOCTOR OF PHILOSOPH

Imagining & Sensing: Understanding and Extending the Vocalist-Voice Relationship Through Biosignal Feedback

The voice is body and instrument. Third-person interpretation of the voice by listeners, vocal teachers, and digital agents is centred largely around audio feedback. For a vocalist, physical feedback from within the body provides an additional interaction. The vocalist’s understanding of their multi-sensory experiences is through tacit knowledge of the body. This knowledge is difficult to articulate, yet awareness and control of the body are innate. In the ever-increasing emergence of technology which quantifies or interprets physiological processes, we must remain conscious also of embodiment and human perception of these processes. Focusing on the vocalist-voice relationship, this thesis expands knowledge of human interaction and how technology influences our perception of our bodies. To unite these different perspectives in the vocal context, I draw on mixed methods from cog- nitive science, psychology, music information retrieval, and interactive system design. Objective methods such as vocal audio analysis provide a third-person observation. Subjective practices such as micro-phenomenology capture the experiential, first-person perspectives of the vocalists them- selves. Quantitative-qualitative blend provides details not only on novel interaction, but also an understanding of how technology influences existing understanding of the body. I worked with vocalists to understand how they use their voice through abstract representations, use mental imagery to adapt to altered auditory feedback, and teach fundamental practice to others. Vocalists use multi-modal imagery, for instance understanding physical sensations through auditory sensations. The understanding of the voice exists in a pre-linguistic representation which draws on embodied knowledge and lived experience from outside contexts. I developed a novel vocal interaction method which uses measurement of laryngeal muscular activations through surface electromyography. Biofeedback was presented to vocalists through soni- fication. Acting as an indicator of vocal activity for both conscious and unconscious gestures, this feedback allowed vocalists to explore their movement through sound. This formed new perceptions but also questioned existing understanding of the body. The thesis also uncovers ways in which vocalists are in control and controlled by, work with and against their bodies, and feel as a single entity at times and totally separate entities at others. I conclude this thesis by demonstrating a nuanced account of human interaction and perception of the body through vocal practice, as an example of how technological intervention enables exploration and influence over embodied understanding. This further highlights the need for understanding of the human experience in embodied interaction, rather than solely on digital interpretation, when introducing technology into these relationships

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.