Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Quadrature Control-Bounded ADCs

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated by considering band-pass analog-to-digital conversion. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations for a variety of filter orders, notch-filter frequencies, and oversampling ratios. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.Comment: 5 pages, 6 figures, submitted to ISCAS 202

Modeling a IF double sampling bandpass switched capacitor ΣΔ ADC with a symmetric noise transfer function for WiMAX/WLAN

4G technology aims to revolutionize private and professional communication with its ubiquity and high-speed transmission (averaging 100Mbps). WiMAX and WLAN are two of the high speed access technologies to be used in the 4G mobile communication. Apropos to their high bandwidths, oversampling converters, e.g.ΣΔ ADCs, used for these standards would entail high levels of power consumption. Double sampling technique used in ΣΔ ADCs help in reducing the power consumption, since the actual sampling rate is only half the sampling frequency required to achieve a target resolution. But for conventional modulators, with low pass noise transfer functions (NTF), this benefit is hampered by the introduction of folded noise due to the mismatch of sampling capacitances. This paper presents a novel method of designing IF bandpass switched capacitor (SC)ΣΔ modulators with symmetric NTFs. Such a bandpass NTF is formulated with its center frequency at one-fourth the effective sampling frequency. The symmetricity ensures that the folded noise is `noise-shaped' along with the quantization noise. The idea is verified with a discrete time bandpass ΣΔ modulator modeled using Simulink®, including various nonlinearities, viz. clock jitter, opampnonidealities, and capacitive mismatch effects owing to double sampling and use of a multibitquantizer. Behavioral simulations of the proposed non-ideal model for WiMAX and WLAN, with a bandwith of 10MHz and 11MHz, respectively, achieved a peak resolution greater than 10 bits for each of the standards

Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ± 1.65V

Kvadratuuri-sigma-delta-AD-muuntimet: mallintaminen ja signaalinkäsittely

The versatile nature of modern wireless communications and on the other hand the push towards cost-efficiency, have created a demand for flexible radio transceivers. In addition, size and power consumption are critical for mobile solutions, thus setting their own demands for the circuitry. Traditionally in such architectures, the analog-to-digital converter has been seen as a performance bottleneck, limiting the possibilities to harness the full potential of the available digital signal processing techniques and algorithms. Therefore, analog-to-digital conversion based on a quadrature ΣΔ modulator noise shaping has been brought in as a promising possibility. More efficient noise shaping and better suitability for modern receivers applying complex signal processing principles already, compared to real counterpart make the quadrature converter particularly interesting choice. This thesis discusses the main principles of quadrature ΣΔ converter and related signal modeling. In addition to understanding the basic operation, it is crucial to understand the implementation related nonidealities, which can’t be avoided in any true circuit. One of the most important phenomena in this field, concerning the in-phase/quadrature processing in the transceivers, is the nonideal matching of the components on the two rails. Thus, the latter part of the thesis gives a detailed analysis on the mismatch problem in quadrature ΣΔ converters. Thereafter, the analysis is confirmed by computer simulations. Finally, it is shown that the mismatch mentioned above is a real concern, especially under the influence of a mirror frequency blocking signal. This might very well be the case in a wideband radio receiver with reduced analog selectivity. On the other hand, the analysis shows that educated design of the signal transfer function can be efficiently used to mitigate the interference originating from the mirror frequency in case of mismatch in the complex feedback branch of the modulator. In this way, the generated distortion can be reduced without any additional electronics, which would compromise cost-efficiency and other demands. Additionally, it is pointed out that independent frequency domain mirroring of the noise and the signal component sets challenges for traditional compensation algorithms. Thus, there is a call for innovative ideas to mitigate the mirror frequency distortion in quadrature ΣΔ modulators via digital signal processing. In this way the cost-efficiency, power consumption and size requirements wouldn’t be jeopardized due to additional electronics. /Kir10Nykyaikaisen langattoman tiedonsiirron monimuotoisuus, ja toisaalta tarve kustannustehokkuuteen, ovat luoneet tarpeen joustaville radiolähetin-vastaanottimille. Mobiilipäätelaitteissa myös koko ja virrankulutus ovat tärkeässä asemassa, asettaen näin omat vaatimuksensa laitteistolle. Tällaisissa rakenteissa analogia-digitaalimuunninten suorituskykyä on pitkään pidetty pullonkaulana nykyaikaisten digitaalisten signaalinkäsittelytekniikoiden tarjoaman potentiaalin hyödyntämiselle. Tämän seurauksena kvadratuuri ΣΔ-modulaattoriin perustuva analogia-digitaalimuunnos on esitetty lupaavana ratkaisuna. Reaaliseen rakenteeseen perustuvaa vastinetta tehokkaampi kohinanmuokkaus ja parempi sopivuus moderneihin kvadratuurivastaanottimiin, joissa hyödynnetään kompleksista signaalinkäsittelyä jo valmiiksi, tekevät muuntimesta erityisen mielenkiintoisen vaihtoehdon. Tässä diplomityössä esitellään kvadratuuri-ΣΔ-muunnoksen perusperiaatteet ja siihen liittyvät signaalimallit. Tämän lisäksi on myös tärkeää, perustoiminnallisuuden ymmärtämisen lisäksi, tiedostaa todelliseen piiritoteutukseen liittyvät väistämättömät epäideaalisuudet. I/Q prosessointia hyödyntävissä radiolaitteissa yksi tärkeimmistä tämän tyyppisistä ilmiöistä on kahden haaran välinen epäsovitus. Tästä johtuen sovitusongelma kvadratuuri ΣΔ muuntimissa analysoidaan tarkasti ja tietokonesimulaatioilla varmennetut tulokset esitetään tämän diplomityön loppupuolella. Työssä osoitetaan, että yllä mainittu epäsovitus on todellinen huolenaihe, erityisesti voimakkaan häiritsevän signaalin ollessa läsnä peilitaajuudella. Tällainen tilanne saattaa toteutua erityisesti laajakaistaisessa vastaanottimessa, jossa analogista selektiivisyyttä on pyritty vähentämään. Toisaalta analyysi osoittaa, että älykkäästi suunniteltu signaalisiirtofunktio auttaa tehokkaasti poistamaan modulaattorin takaisinkytkentähaarassa sijaitsevan epäsovituksen aiheuttamaa häiriötä. Tällä tavoin syntynyttä vääristymää pystytään vähentämään ilman ylimääräistä elektroniikkaa, jolloin kustannustehokkuudesta, tai muista vaatimuksista ei tarvitse tinkiä. Tämän lisäksi osoitetaan, että signaali- ja kohinakomponenttien toisistaan riippumaton peilaantuminen taajuuden suhteen luo haasteita perinteisille korjausalgoritmeille. Näin ollen kvadratuuri-ΣΔ-modulaattoreiden peilitaajuushäiriön hallitsemiseksi digitaalisen signaalinkäsittelyn keinoin tarvitaan uudenlaisia innovaatioita. Tällä tavoin voitaisiin myös välttää analogisen lisäelektroniikan aiheuttama kustannustehokkuus-, virrankulutus- ja kokovaatimusten vaarantuminen

Transmitter architectures with digital modulators, D/A converters and switching-mode power amplifiers

This thesis is composed of nine publications and an overview of the research topic, which also summarises the work. The research described in this thesis focuses on research into the digitalisation of wireless communication base station transmitters. In particular it has three foci: digital modulation, D/A conversion and switching-mode power amplification. The main interest in the implementation of these circuits is in CMOS. The work summarizes the designs of several circuit blocks of a wireless transmitter base station. In the baseband stage, a multicarrier digital modulator that combines multiple modulated signals at different carrier frequencies digitally at baseband, and a multimode digital modulator that can be operated for three different communications standards, are implemented as integrated circuits. The digital modulators include digital power ramping and power level control units for transmission bursts. The upconversion of the baseband signal is implemented using an integrated digital quadrature modulator. The work presented provides insight into the digital-to-analogue interface in the transmitters. This interface is studied both by implementing an intermediate frequency D/A converter in BiCMOS technology and bandpass Delta-Sigma modulator-based D/A conversion in CMOS technology. Finally, the last part of the work discusses switching-mode power amplifiers which are experimented with both as discrete and integrated implementations in conjunction with 1-bit Delta-Sigma modulation and pulse-width modulation as input signal generation methods.Tämä väitöskirja koostuu yhdeksästä julkaisusta ja tutkimusaiheen yhteenvedosta. Väitöskirjassa esitetty tutkimus keskittyy langattaman viestinnän tukiasemien lähettimien digitalisoinnin tutkimukseen. Yksityiskohtaisemmin tutkimusalueet ovat: digitaalinen modulaatio, D/A muunnos ja kytkinmuotoiset tehovahvistimet. Näiden elektronisten piirien toteutuksessa keskitytään CMOS teknologiaan. Työ vetää yhteen useiden langattoman viestinnän tukiasemien lähettimien piirilohkojen suunnittelun. Kantataajuusasteella toteutetaan integroituna piirinä monikantoaaltoinen digitaalinen modulaattori, joka yhdistää useita moduloituja signaaleja eri kantoaalloilla digitaalisesti ja monistandardi digitaalinen modulaatori, joka tukee kolmea eri viestintästandardia. Digitaaliset modulaattoripiirit sisältävät digitaalisen tehoramping ja tehotason säätöyksikön lähetyspurskeita varten. Kantataajuussignaalin ylössekoitus toteutetaan integroitua digitaalista kvadratuurimodulaattoria käyttäen. Esitetty työ antaa näkemystä lähettimien digitalia-analogia rajapintaan, jota tutkitaan toteuttamalla välitaajuinen D/A muunnin BiCMOS teknologialla ja päästökaistainen Delta-Sigma-modulaattoripohjainen D/A muunnin CMOS teknologialla. Lopuksi työn viimeinen osa käsittelee kytkinmuotoisia tehovahvistimia, joita tutkitaan kokeellisesti sekä erilliskompontein toteutettuina piirein että integroiduin piirein toteutettuina käyttäen sisääntulosignaalin muodostamismenetemänä yksibittistä Delta-Sigma-modulaatiota ja pulssin leveys modulaatiota.reviewe

A Control-Bounded Quadrature Leapfrog ADC

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.Comment: 13 pages and 16 figure

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique