Investigations on the vulnerability of advanced CMOS technologies to MGy dose environments

This paper investigates the TID sensitivity of silicon-based technologies at several MGy irradiation doses to evaluate their potential for high TID-hardened circuits. Such circuits will be used in several specific applications suc as safety systems of current or future nuclear power plants considering various radiation environments including normal and accidental operating conditions, high energy physics instruments, fusion experiments or deep space missions. Various device designs implemented in well established bulk silicon and Partially Depleted SOI technologies are studied here up to 3 MGy. Furthermore, new insights are given on the vulnerability of more advanced technologies including planar Fully Depleted SOI and multiple-gate SOI transistors at such high dose. Potential of tested technologies are compared and discussed for stand-alone integrated circuits

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

3-D Quantum Numerical Simulation of Transient Response in Multiple-Gate Nanowire MOSFETs Submitted to Heavy Ion Irradiation

International audienc

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Journal of Telecommunications and Information Technology, 2007, nr 2

kwartalni

Study of Radiation Tolerant Storage Cells for Digital Systems

Single event upsets (SEUs) are a significant reliability issue in semiconductor devices. Fully Depleted Silicon-on-Insulator (FDSOI) technologies have been shown to exhibit better SEU performance compared to bulk technologies. This is attributed to the thin Silicon (Si) layer on top of a Buried Oxide (BOX) layer, which allows each transistor to function as an insulated Si island, thus reducing the threat of charge-sharing. Moreover, the small volume of the Si in FDSOI devices results in a reduction of the amount of charge induced by an ion strike. The effects of Total Ionizing Dose (TID) on integrated circuits (ICs) can lead to changes in gate propagation delays, leakage currents, and device functionality. When IC circuits are exposed to ionizing radiation, positive charges accumulate in the gate oxide and field oxide layers, which results in reduced gate control and increased leakage current. TID effects in bulk technologies are usually simpler due to the presence of only one gate oxide layer, but FDSOI technologies have a more complex response to TID effects because of the additional BOX layer. In this research, we aim to address the challenges of developing cost-effective electronics for space applications by bridging the gap between expensive space-qualified components and high-performance commercial technologies. Key research questions involve exploring various radiation-hardening-by-design (RHBD) techniques and their trade-offs, as well as investigating the feasibility of radiation-hardened microcontrollers. The effectiveness of RHBD techniques in mitigating soft errors is well-established. In our study, a test chip was designed using the 22-nm FDSOI process, incorporating multiple RHBD Flip-Flop (FF) chains alongside a conventional FF chain. Three distinct types of ring oscillators (ROs) and a 256 kbit SRAM was also fabricated in the test chip. To evaluate the SEU and TID performance of these designs, we conducted multiple irradiation experiments with alpha particles, heavy ions, and gamma-rays. Alpha particle irradiation tests were carried out at the University of Saskatchewan using an Americium-241 alpha source. Heavy ion experiments were performed at the Texas A&M University Cyclotron Institute, utilizing Ne, Ar, Cu, and Ag in a 15 MeV/amu cocktail. Lastly, TID experiments were conducted using a Gammacell 220 Co-60 chamber at the University of Saskatchewan. By evaluating the performance of these designs under various irradiation conditions, we strive to advance the development of cost-effective, high-performance electronics suitable for space applications, ultimately demonstrating the significance of this project. When exposed to heavy ions, radiation-hardened FFs demonstrated varying levels of improvement in SEU performance, albeit with added power and timing penalties compared to conventional designs. Stacked-transistor DFF designs showed significant enhancement, while charge-cancelling and interleaving techniques further reduced upsets. Guard-gate (GG) based FF designs provided additional SEU protection, with the DFR-FF and GG-DICE FF designs showing zero upsets under all test conditions. Schmitt-trigger-based DFF designs exhibited improved SEU performance, making them attractive choices for hardening applications. The 22-nm FDSOI process proved more resilient to TID effects than the 28-nm process; however, TID effects remained prominent, with increased leakage current and SRAM block degradation at high doses. These findings offer valuable insights for designers aiming to meet performance and SER specifications for circuits in radiation environments, emphasizing the need for additional attention during the design phase for complex radiation-hardened circuits

A study of the device characteristics of a novel body-contact SOI structure.

Lau Wai Kwok.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references.Acknowledgement --- p.ivAbstract --- p.vChapter Chapter 1 --- Introduction --- p.1-1Chapter 1.1 --- Perspective --- p.1-1Chapter 1.2 --- MEDICI - The Simulation Package --- p.1 -2Chapter 1.3 --- Overview --- p.1-3Chapter Chapter 2 --- The Emergence of SOI Devices --- p.2-1Chapter 2.1 --- Introduction --- p.2-1Chapter 2.2 --- Advantages of SOI Devices --- p.2-1Chapter 2.2.1 --- Reliability Improvement --- p.2-2Chapter 2.2.2 --- Total Isolation --- p.2-3Chapter 2.2.3 --- Improved Junction Structure --- p.2-4Chapter 2.2.4 --- Integrated Device Structure --- p.2-5Chapter 2.3 --- Categories of SOI Devices --- p.2-6Chapter 2.3.1 --- Thick Film SOI Devices --- p.2-7Chapter 2.3.2 --- Thin Film SOI Devices --- p.2-8Chapter 2.3.3 --- Medium Film SOI Devices --- p.2-8Chapter 2.4 --- Drawbacks of SOI Devices --- p.2-9Chapter 2.4.1 --- Floating Body Effects --- p.2-9Chapter 2.4.2 --- Parasitic Bipolar Effects --- p.2-11Chapter 2.4.3 --- Cost --- p.2-15Chapter 2.5 --- Manufacturing Methods --- p.2-16Chapter 2.5.1 --- Epitaxy-Based Method --- p.2-16Chapter 2.5.2 --- Recrystallization-Based Method --- p.2-18Chapter 2.5.3 --- Wafer Bonding Based Method --- p.2-19Chapter 2.5.4 --- Oxidation Based Method --- p.2-20Chapter 2.5.5 --- Implantation Based Method --- p.2-22Chapter 2.6 --- Future Trend --- p.2-22Chapter 2.7 --- The Quest for Silicon-On-Nitride Structure --- p.2-23Chapter Chapter 3 --- Description of Body-Contact SOI Structure --- p.3-1Chapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Current Status of Body-Contact SOI Structure --- p.3-1Chapter 3.3 --- The Body-Contact SOI Structure to be studied --- p.3-4Chapter 3.4 --- Impact on Device Fabrication --- p.3-7Chapter 3.4.1 --- Fabrication of Conventional Bulk CMOS --- p.3-7Chapter 3.4.2 --- Fabrication of Conventional SOI CMOS --- p.3-8Chapter 3.4.3 --- Fabrication of BC SOI CMOS --- p.3-10Chapter Chapter 4 --- Device Simulations --- p.4-1Chapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- MEDICI --- p.4-1Chapter 4.2.1 --- Basic Equations --- p.4-2Chapter 4.2.2 --- Solution Methods --- p.4-3Chapter 4.2.3 --- Initial Guess --- p.4-6Chapter 4.2.4 --- Grid Allocations --- p.4-7Chapter 4.2.5 --- Source File --- p.4-8Chapter 4.3 --- Structures for Simulations --- p.4-9Chapter 4.3.1 --- l.2μm NMOS Bulk (LDD) --- p.4-9Chapter 4.3.2 --- 1.2μm SOI(O) NMOS 1000/3500 NBC --- p.4-11Chapter 4.3.3 --- 1.2μm SOI(N) NMOS 1000/3500 NBC --- p.4-12Chapter 4.3.4 --- 1.2μm SOI(O) NMOS 1000/3500 WBC --- p.4-13Chapter 4.3.5 --- 1.2μm SOI(N) NMOS 1000/3500 WBC --- p.4-14Chapter 4.4 --- Summary --- p.4-14Chapter Chapter 5 --- Simulation Results --- p.5-1Chapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- Comparisons of Different Structures --- p.5-1Chapter 5.2.1 --- Impurity Profiles of Structures --- p.5-2Chapter 5.2.2 --- Body Effect --- p.5-10Chapter 5.2.3 --- Breakdown Voltage and Transistor Current Driving --- p.5-16Chapter 5.2.4 --- Transconductance and Mobility --- p.5-20Chapter 5.2.5 --- Subthreshold Swing --- p.5-23Chapter 5.3 --- Dependence on Key Structure Parameters --- p.5-29Chapter 5.3.1 --- Dependence on Insulator Thickness --- p.5-29Chapter 5.3.2 --- Dependence on Silicon Overlayer Thickness --- p.5-34Chapter 5.3.3 --- Dependence on Size of Body-Contact --- p.5-37Chapter 5.4 --- Summary --- p.5-40Chapter Chapter 6 --- Reduction of Latch-up Susceptibility --- p.6-1Chapter 6.1 --- Introduction --- p.6-1Chapter 6.2 --- Construction of a p-channel MOS Transistor --- p.6-2Chapter 6.2.1 --- Threshold Voltage and Body Effect --- p.6-3Chapter 6.2.2 --- I-V Characteristics --- p.6-3Chapter 6.2.3 --- Transconductance --- p.6-5Chapter 6.2.4 --- Subthreshold Swing --- p.6-5Chapter 6.3 --- Mechanism of Latch-up in CMOS --- p.6-6Chapter 6.4 --- Construction of a CMOS Invertor for Simulation --- p.6-10Chapter 6.5 --- Latch-up Susceptibility Dependence --- p.6-16Chapter 6.5.1 --- Dependence on Insulator Thickness --- p.6-16Chapter 6.5.2 --- Dependence on N-well Depth --- p.6-19Chapter 6.5.3 --- Dependence on Transistor Separation --- p.6-22Chapter 6.5.4 --- Dependence on Size of Body-Contact --- p.6-25Chapter 6.6 --- Summary --- p.6-28Chapter Chapter 7 --- Conclusions --- p.7-1Chapter 7.1 --- Summary --- p.7-1Chapter 7.2 --- Recommendation --- p.7-3ReferenceAppendix