Single event upsets (SEUs) are a significant reliability issue in semiconductor devices. Fully Depleted Silicon-on-Insulator (FDSOI) technologies have been shown to exhibit better SEU performance compared to bulk technologies. This is attributed to the thin Silicon (Si) layer on top of a Buried Oxide (BOX) layer, which allows each transistor to function as an insulated Si island, thus reducing the threat of charge-sharing. Moreover, the small volume of the Si in FDSOI devices results in a reduction of the amount of charge induced by an ion strike.
The effects of Total Ionizing Dose (TID) on integrated circuits (ICs) can lead to changes in gate propagation delays, leakage currents, and device functionality. When IC circuits are exposed to ionizing radiation, positive charges accumulate in the gate oxide and field oxide layers, which results in reduced gate control and increased leakage current. TID effects in bulk technologies are usually simpler due to the presence of only one gate oxide layer, but FDSOI technologies have a more complex response to TID effects because of the additional BOX layer.
In this research, we aim to address the challenges of developing cost-effective electronics for space applications by bridging the gap between expensive space-qualified components and high-performance commercial technologies. Key research questions involve exploring various radiation-hardening-by-design (RHBD) techniques and their trade-offs, as well as investigating the feasibility of radiation-hardened microcontrollers.
The effectiveness of RHBD techniques in mitigating soft errors is well-established. In our study, a test chip was designed using the 22-nm FDSOI process, incorporating multiple RHBD Flip-Flop (FF) chains alongside a conventional FF chain. Three distinct types of ring oscillators (ROs) and a 256 kbit SRAM was also fabricated in the test chip. To evaluate the SEU and TID performance of these designs, we conducted multiple irradiation experiments with alpha particles, heavy ions, and gamma-rays. Alpha particle irradiation tests were carried out at the University of Saskatchewan using an Americium-241 alpha source. Heavy ion experiments were performed at the Texas A&M University Cyclotron Institute, utilizing Ne, Ar, Cu, and Ag in a 15 MeV/amu cocktail. Lastly, TID experiments were conducted using a Gammacell 220 Co-60 chamber at the University of Saskatchewan. By evaluating the performance of these designs under various irradiation conditions, we strive to advance the development of cost-effective, high-performance electronics suitable for space applications, ultimately demonstrating the significance of this project.
When exposed to heavy ions, radiation-hardened FFs demonstrated varying levels of improvement in SEU performance, albeit with added power and timing penalties compared to conventional designs. Stacked-transistor DFF designs showed significant enhancement, while charge-cancelling and interleaving techniques further reduced upsets. Guard-gate (GG) based FF designs provided additional SEU protection, with the DFR-FF and GG-DICE FF designs showing zero upsets under all test conditions. Schmitt-trigger-based DFF designs exhibited improved SEU performance, making them attractive choices for hardening applications. The 22-nm FDSOI process proved more resilient to TID effects than the 28-nm process; however, TID effects remained prominent, with increased leakage current and SRAM block degradation at high doses. These findings offer valuable insights for designers aiming to meet performance and SER specifications for circuits in radiation environments, emphasizing the need for additional attention during the design phase for complex radiation-hardened circuits
