Selective harmonic mitigation based two-scale frequency control of cascaded modified packed U-cell inverters

A new Modified Packed U-Cell (MPUC) converter architecture with cascading is proposed in this paper. To provide an output voltage of 25 levels, the proposed cascaded MPUC needs only twelve power switches and four power sources. The converter comprises two cascaded MPUCs with DC supply in a ratio of 5 : 1. One converter is operating at low frequency (LF) and the other at high frequency (HF) that leads to lower power losses and higher levels. Besides, a variable frequency method is anticipated to produce a 25-level output voltage which has low harmonic content (THD) with the help of Selective Harmonic Mitigation (SHM). The optimum switching angles for SHM are obtained through solving the SHM equations using the Genetic Algorithm (GA). The designed controller is efficient and suitable for applications that require low-frequency operation either in stand-alone or grid-tied. The proposed inverter and its operation procedure have been investigated using MATLAB®/Simulink software, and the findings demonstrate that the proposed inverter output voltage has reduced THD significantly. The simulation results are verified using the typhoon HIL-402 emulator. Also, the power loss analysis is done using PLECS. The maximum efficiency of the converter is found to be around 98.34 %. The simulation results justified the efficiency and viability of low 25-level THD voltages

A Robust Multilevel Inverter Topology for Operation under Fault Conditions

Multilevel inverters (MLIs) are new demanding topologies that have low total harmonic distortion (THD) and low voltage stress across the switches make them ideal for medium and high-power applications. The authenticity of semiconductor devices is one of the main concerns for these MLIs to operate properly. With an increment in the number of switches in multilevel inverters, the pos-sibility of the fault also arises. Hence, a reliable 5- level inverter topology with fault-tolerant ability has been proposed. The proposed topology can withstand against of Open Circuit (OC) fault caused when any single switch fails. The proposed configuration is fault-tolerant and reliable as compared to the conventional multilevel inverters. Simulation of the proposed topology is done in MATLAB-Simulink and PLECS software packages, and the results obtained for normal (pre-fault), during the fault, and post-fault conditions are discussed. Experimental results also prove the proposed cell topology's robustness and effectiveness in tolerating OC faults across the switches. Furthermore, a thorough comparison is provided to demonstrate the superiority of the proposed topology in comparison to recently published topologies that have fault-tolerant featurespublishedVersio

Reliability and Performance Improvement of PUC Converter Using a New Single-Carrier Sensor-Less PWM Method with Pseudo Reference Functions

A new single-carrier sensor-less pulsewidth modulation (PWM) method using suggested pseudo reference functions is proposed for packed U-cell (PUC) converter to improve performance and reliability of the PUC converter. It is composed of one PWM carrier signal and two suggested pseudo reference functions. By employing the proposed modulation method, the PUC dc capacitor voltage ripple is substantially decreased, and faster sensor-less capacitor voltage balancing is obtained. Moreover, the power losses are evenly distributed among all power switches. Consequently, notable reduction of the PUC dc capacitor voltage ripple and even distribution of the power loss among switches enhance the PUC converter\u27s reliability and lifetime. In addition, odd multiples of the switching harmonic clusters are eliminated from the output voltage; thus, the values of output passive filter components are halved. Hence, applying the proposed single-carrier sensor-less PWM method remarkably improves the performance, power density, reliability, and lifetime of the PUC converter and notably simplifies implementation of the switching pattern. Provided experimental results and comparisons as well as reliability analysis verify the viability and effectiveness of the proposed PWM method

A Compact Design Using GaN Semiconductor Devices for a Flying Capacitor Five-Level Inverter

Multilevel inverters (MLIs) based on the flying capacitor (FC) concept are beneficial in many renewable energy-based applications due to their compactness, low current stress on semiconductor devices, and reasonable thermal behavior for high-power applications. However, the recently developed FC-based topologies suffer from half dc-link voltage utilization and a variable high-frequency common-mode voltage (HF-CMV). The aim of this paper is to propose an FC-based family of MLIs with a five-level (5L) output voltage, full dc-link voltage utilization, and low HF-CMV. Using redundant states and the phase-shifted sinusoidal PWM technique, the value of the flying capacitor has been reduced significantly. The performance of the converter has been verified using Gallium Nitride (GaN) power switches. Circuit description and a brief comparative study with existing MLIs are given to justify the suitability of the topology

THD Analysis of a Seven, Nine, and Eleven Level Cascaded H-Bridge Multilevel Inverter for Different Loads

A multilevel inverter is implemented for generating the required staircase AC voltage of output from various steps of voltages of DC sources. The multilevel inverter gives a better harmonic spectrum and a compatible quality of output. This article delves into an analytical analysis of the total harmonic distortion (THD) of different multilevel inverters which employ a multicarrier PWM technique. This technique is implemented for operating the switches at their respective angle of conduction. This paper deals with various cascaded H-Bridge multilevel inverters (CMI) with various loads that are modelled by implementing the MATLAB/Simulink platform. The output gives a better result of the proposed model in terms that it is helpful towards reducing the THD and the losses of switching

Modulation with metaheuristic approach for cascaded-MPUC49 asymmetrical inverter with boosted output

This work introduces a 49-level Asymmetrical Inverter (AMLI) with boosted output based on the cascaded operation of two 7-Level Modified Packed U-Cell inverters (MPUC-7). The converter is capable of operation with a boosted voltage of up to 1.714 times the maximum DC voltage employed. It requires only 12 active switches and 4 voltage sources. With the sources set in the ratio of 14:7:2:1, the 7-level output of the two converters is so utilized that the 72 = 49-level output voltage is generated across the load. A detailed explanation of level formation is discussed. This converter is operated using an Artificial Neural Network (ANN) which is trained for the harmonic elimination in the output voltage waveform. For the calculation of optimum angles, a meta-heuristic based Genetic Algorithm (GA) technique is employed. The generation of 49-level output requires 24 transitions in one quarter of a cycle. All these angles are generated for various desired output voltages, and the ANN is trained offline for the same. The converter and its control are simulated in MATLAB/Simulink environment, and the results are verified on the experimental setup. The multilevel output thus obtained is nearly sinusoidal and the Total Harmonic Distortion (THD) thus produced is under the specified limit of IEEE.This work was supported in part by the Qatar University-Marubeni Concept to Prototype Development Research from the Qatar University under Grant M-CTP-CENG-2020-2, and in part by the Qatar National Library, Doha, Qatar.Scopu

Switched-capacitor integrated single-phase (2n+1)-levels boost inverter for grid-tied photovoltaic (pv) applications

© 2019 IEEE. This paper presents a switched-capacitor integrated (2N+1)-level (N≥2) boost inverter for single-phase photovoltaic (PV) applications. It consists of N modular switching cells, where each cell consists of two switched capacitors and three active switching elements. A boost converter at the front side of the switching cells helps to maintain the capacitor voltage balance during different operation modes. With this arrangement, the inverter is capable to generate 2N+1 output voltage levels, and able to accommodate a wide range of input voltage. Detailed analysis followed by simulation and experimental results of a 5-level inverter as an example is presented to verify the proposed concept. Further, comparison with other multilevel inverter topologies is presented to show the merit of the proposed concept