High Speed CMOS VCO For Advanced Communications [TK7871.99.M99 C435 2003 f rb][Microfiche 7271].

Peningkatan keperluan bagi komunikasi tanpa wayar dalam suara dan data telah memotivasikan kerja-kerja untuk meningkatkan tahap intregrasi dalam pemancar-penerima berfrekuensi radio (RF) baru-baru ini. The fast growing demand of wireless communications for voice and data has driven recent efforts to dramatically increase the level of integration in RF transceivers

Attosecond Precision Multi-km Laser-Microwave Network

Synchronous laser-microwave networks delivering attosecond timing precision are highly desirable in many advanced applications, such as geodesy, very-long-baseline interferometry, high-precision navigation and multi-telescope arrays. In particular, rapidly expanding photon science facilities like X-ray free-electron lasers and intense laser beamlines require system-wide attosecond-level synchronization of dozens of optical and microwave signals up to kilometer distances. Once equipped with such precision, these facilities will initiate radically new science by shedding light on molecular and atomic processes happening on the attosecond timescale, such as intramolecular charge transfer, Auger processes and their impact on X-ray imaging. Here, we present for the first time a complete synchronous laser-microwave network with attosecond precision, which is achieved through new metrological devices and careful balancing of fiber nonlinearities and fundamental noise contributions. We demonstrate timing stabilization of a 4.7-km fiber network and remote optical-optical synchronization across a 3.5-km fiber link with an overall timing jitter of 580 and 680 attoseconds RMS, respectively, for over 40 hours. Ultimately we realize a complete laser-microwave network with 950-attosecond timing jitter for 18 hours. This work can enable next-generation attosecond photon-science facilities to revolutionize many research fields from structural biology to material science and chemistry to fundamental physics.Comment: 42 pages, 13 figure

Theory of phaselock techniques as applied to aerospace transponders

Phaselock techniques as applied to aerospace transponder

Timing Signals and Radio Frequency Distribution Using Ethernet Networks for High Energy Physics Applications

Timing networks are used around the world in various applications from telecommunications systems to industrial processes, and from radio astronomy to high energy physics. Most timing networks are implemented using proprietary technologies at high operation and maintenance costs. This thesis presents a novel timing network capable of distributed timing with subnanosecond accuracy. The network, developed at CERN and codenamed “White- Rabbit”, uses a non-dedicated Ethernet link to distribute timing and data packets without infringing the sub-nanosecond timing accuracy required for high energy physics applications. The first part of this thesis proposes a new digital circuit capable of measuring time differences between two digital clock signals with sub-picosecond time resolution. The proposed digital circuit measures and compensates for the phase variations between the transmitted and received network clocks required to achieve the sub-nanosecond timing accuracy. Circuit design, implementation and performance verification are reported. The second part of this thesis investigates and proposes a new method to distribute radio frequency (RF) signals over Ethernet networks. The main goal of existing distributed RF schemes, such as Radio-Over-Fibre or Digitised Radio-Over-Fibre, is to increase the bandwidth capacity taking advantage of the higher performance of digital optical links. These schemes tend to employ dedicated and costly technologies, deemed unnecessary for applications with lower bandwidth requirements. This work proposes the distribution of RF signals over the “White-Rabbit” network, to convey phase and frequency information from a reference base node to a large numbers of remote nodes, thus achieving high performance and cost reduction of the timing network. Hence, this thesis reports the design and implementation of a new distributed RF system architecture; analysed and tested using a purpose-built simulation environment, with results used to optimise a new bespoke FPGA implementation. The performance is evaluated through phase-noise spectra, the Allan-Variance, and signalto- noise ratio measurements of the distributed signals

A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units

This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synchronization error due to the local oscillator triggering the on-board timer. The SC has been implemented into a PMU prototype developed within the OpenPMU project using a BeagleBone Black (BBB) board. The distinctive feature of the proposed solution is its ability to track an input Pulse-Per-Second (PPS) reference with good long-term stability and with no need for specific on-board synchronization circuitry. Indeed, the SC implementation relies only on one co-processor for real-time application and requires just an input PPS signal that could be distributed from a single substation clock

Array E ALSEP Command Decoder data demodulator analysis

This report presents the design equations used in the selection of part values, the theoretical performance for the specified uplink transmission, and the theoretical response of the command decoder with no uplink transmission. The theoretical results for no uplink transmission are compared to measured data taken on the Design Verification Model, which was presented at the Critical Design Review.prepared by V. Kemp, prepared by B. McLeod

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort