Coherent receiver design and analysis for interleaved division multiple access (IDMA)

This thesis discusses a new multiuser detection technique for cellular wireless communications. Multiuser communications is critical in cellular systems as multiple terminals (users) transmit to base stations (or wireless infrastructure). Efficient receiver methods are needed to maximise the performance of these links and maximise overall throughput and coverage while minimising inter-cell interference. Recently a new technique, Interleave-Division Multiple Access (IDMA), was developed as a variant of direct-sequence code division multiple access (DS-CDMA). In this new scheme users are separated by user specific interleavers, and each user is allocated a low rate code. As a result, the bandwidth expansion is devoted to the low rate code and not weaker spreading codes. IDMA has shown to have significant performance gains over traditional DS-CDMA with a modest increase in complexity. The literature on IDMA primarily focuses on the design of low rate forward error correcting (FEC) codes, as well as channel estimation. However, the practical aspects of an IDMA receiver such as timing acquisition, tracking, block asynchronous detection, and cellular analysis are rarely studied. The objective of this thesis is to design and analyse practical synchronisation, detection and power optimisation techniques for IDMA systems. It also, for the first time, provides a novel analysis and design of a multi-cell system employing a general multiuser receiver. These tools can be used to optimise and evaluate the performance of an IDMA communication system. The techniques presented in this work can be easily employed for DS-CDMA or other multiuser receiver designs with slight modification. Acquisition and synchronisation are essential processes that a base-station is required to perform before user's data can be detected and decoded. For high capacity IDMA systems, which can be heavily loaded and operate close to the channel capacity, the performance of acquisition and tracking can be severely affected by multiple access interference as well as severe drift. This thesis develops acquisition and synchronisation algorithms which can cope with heavy multiple access interference as well as high levels of drift. Once the timing points have been estimated for an IDMA receiver the detection and decoding process can proceed. An important issue with uplink systems is the alignment of frame boundaries for efficient detection. This thesis demonstrates how a fully asynchronous system can be modelled for detection. This thesis presents a model for the frame asynchronous IDMA system, and then develops a maximum likelihood receiver for the proposed system. This thesis develops tools to analyse and optimise IDMA receivers. The tools developed are general enough to be applied to other multiuser receiver techniques. The conventional EXIT chart analysis of unequal power allocated multiuser systems use an averaged EXIT chart analysis for all users to reduce the complexity of the task. This thesis presents a multidimensional analysis for power allocated IDMA, and shows how it can be utilised in power optimisation. Finally, this work develops a novel power zoning technique for multicell multiuser receivers using the optimised power levels, and illustrates a particular example where there is a 50% capacity improvement using the proposed scheme. -- provided by Candidate

FPGA BASED TIMING MODULE AND OPTICAL COMMUNICATION CARD DESIGN FOR SPALLATION NEUTRON SOURCE

The Timing Module and Optical Communication Card (OCC) are used for acquisition of neutron event data by the instrument systems at the Spallation Neutron Source (SNS) neutron scattering facility. The instrument systems produce a very large flux of neutrons of varying energies over a short time period through the spallation process. The Timing Module and OCC require high-bandwidth communication to ensure high-speed data movement to the memory in the data collection system without loss of neutron data. The existing implementations use a standard PCI-X bus interface to transfer the data between the cards and the host computer. The data processing on the existing cards is implemented in a Xilinx Virtex-II FPGA. The bandwidth restrictions of the PCI-X bus and the logic constraints of the Virtex-II FPGA have resulted in limited capabilities of the instrument systems. New designs for the timing and communication modules that will improve performance, avoid data loss, and provide for future logic expansion are desired. In this project, we redesign the Timing Module and OCC moving from a PCI-X to PCI-Express bus interface to improve the data acquisition bandwidth. The new design also uses a Xilinx Virtex-5 FPGA to allow more channels to be processed per card and provide for further expansion. Further, the Virtex-5 device also has an embedded PCI-Express Hard IP core. This internal core simplifies the Printed Circuit Board (PCB) design since there is no external PCI interface chip required and decreases the probability of errors between the PCI interface and user logic design. The Timing Module implements a simple PCI Express read and write for the data transfer. The OCC requires a higher data rate than the Timing Module and therefore uses a more complex bus master direct memory access (DMA) for the endpoint PCI-Express block, which allows for lower CPU utilization and higher performance. New user logic interfaces were designed to integrate the PCI-Express endpoint with the Timing Module and the OCC logic designs. A single PCB was designed to function as both the Timing Module and OCC. The logic designs were verified by both functional simulation and in-system JTAG signal capture on the new PCB. The results indicate that our design provides efficient data transfer, higher throughput, and scalability, benefitting both modules and meeting design requirements

A High-performance, Energy-efficient Modular DMA Engine Architecture

Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs) are critically needed to transfer data independently of the processing elements, hiding latency and achieving high throughput even for complex access patterns to high-latency memory. With the prevalence of heterogeneous systems, DMAEs must operate efficiently in increasingly diverse environments. This work proposes a modular and highly configurable open-source DMAE architecture called intelligent DMA (iDMA), split into three parts that can be composed and customized independently. The front-end implements the control plane binding to the surrounding system. The mid-end accelerates complex data transfer patterns such as multi-dimensional transfers, scattering, or gathering. The back-end interfaces with the on-chip communication fabric (data plane). We assess the efficiency of iDMA in various instantiations: In high-performance systems, we achieve speedups of up to 15.8x with only 1 % additional area compared to a base system without a DMAE. We achieve an area reduction of 10 % while improving ML inference performance by 23 % in ultra-low-energy edge AI systems over an existing DMAE solution. We provide area, timing, latency, and performance characterization to guide its instantiation in various systems.Comment: 14 pages, 14 figures, accepted by an IEEE journal for publicatio

A DSP equipped digitizer for online analysis of nuclear detector signals

In the framework of the NUCL-EX collaboration, a DSP equipped fast digitizer has been implemented and it has now reached the production stage. Each sampling channel is implemented on a separate daughter-board to be plugged on a VME mother-board. Each channel features a 12-bit, 125 MSamples/s ADC and a Digital Signal Processor (DSP) for online analysis of detector signals. A few algorithms have been written and successfully tested on detectors of different types (scintillators, solid-state, gas-filled), implementing pulse shape discrimination, constant fraction timing, semi-Gaussian shaping, gated integration

A New Scheme for Spreading & De-spreading in the Direct Sequence Spread Spectrum Mechanism

Direct Sequence Spread Spectrum (DSSS) and Frequency Hopping Spread Spectrum (FHSS) techniques are widely used to implement code-division multiple access (CDMA) in wireless communication systems.  Both DSSS and FHSS systems help reducing the effects of interference on the transmitted information making it robust against channel impairments.  DSSS uses a signal bandwidth that is much broader than the information signal bandwidth.  Traditionally, the wide band signal is generated by multiplying the narrowband information signal with a binary code, often designated as a spreading code, to generate the wideband signal that is transmitted. The original information signal can be recreated at the receiver by multiplying the received wideband signal by the same binary code (now designated as a de-spreading code) used to generate the wideband transmitted signal.  To extract the original information signal, the spreading and de-spreading codes must be in synchronism at the receiver and amplitude match with each other.  A new modification for the direct sequence spread spectrum is proposed in this paper. The mechanism introduced in this approach implicates generating the wideband signal by circularly shifting the spreading code (PN) by n places, where n represents the value of the current byte of information signal. The yielded signal is modulated using BPSK modulator before transmitting it.  The original information signal is extracted at the receiver by correlating the received signal (which is actually the original spread sequence circularly shifted by n places) with a locally generated replica of the spreading code.  The position of the maximum value of the cross-correlation vector represents the value of the information signal byte.  The proposed configuration has been implemented using Simulink simulator and the obtained results show that its performance is identical with the conventional DSSS

Initial synchronisation of wideband and UWB direct sequence systems: single- and multiple-antenna aided solutions

This survey guides the reader through the open literature on the principle of initial synchronisation in single-antenna-assisted single- and multi-carrier Code Division Multiple Access (CDMA) as well as Direct Sequence-Ultra WideBand (DS-UWB) systems, with special emphasis on the DownLink (DL). There is a paucity of up-to-date surveys and review articles on initial synchronization solutions for MIMO-aided and cooperative systems - even though there is a plethora of papers on both MIMOs and on cooperative systems, which assume perfect synchronization. Hence this paper aims to ?ll the related gap in the literature

Adaptive implementation of turbo multi-user detection architecture

MULTI-access techniques have been adopted widely for communications in underwater acoustic channels, which present many challenges to the development of reliable and practical systems. In such an environment, the unpredictable and complex ocean conditions cause the acoustic waves to be affected by many factors such as limited bandwidth, large propagation losses, time variations and long latency, which limit the usefulness of such techniques. Additionally, multiple access interference (MAI) signals and poor estimation of the unknown channel parameters in the presence of limited training sequences are two of the major problems that degrade the performance of such technologies. In this thesis, two different single-element multi-access schemes, interleave division multiple access (IDMA) and code division multiple access (CDMA), employing decision feedback equalization (DFE) and soft Rake-based architectures, are proposed for multi-user underwater communication applications. By using either multiplexing pilots or continuous pilots, these adaptive turbo architectures with carrier phase tracking are jointly optimized based on the minimum mean square error (MMSE) criterion and adapted iteratively by exchanging soft information in terms of Log-Likelihood Ratio (LLR) estimates with the single-user’s channel decoders. The soft-Rake receivers utilize developed channel estimation and the detection is implemented using parallel interference cancellation (PIC) to remove MAI effects between users. These architectures are investigated and applied to simulated data and data obtained from realistic underwater communication trials using off-line processing of signals acquired during sea-trials in the North Sea. The results of different scenarios demonstrate the penalty in performance as the fading induces irreducible error rates that increase with channel delay spread and emphasize the benefits of using coherent direct adaptive receivers in such reverberant channels. The convergence behaviour of the detectors is evaluated using EXIT chart analyses and issues such as the adaptation parameters and their effects on the performance are also investigated. However, in some cases the receivers with partial knowledge of the interleavers’ patterns or codes can still achieve performance comparable to those with full knowledge. Furthermore, the thesis describes implementation issues of these algorithms using digital signal processors (DSPs), such as computational complexity and provides valuable guidelines for the design of real time underwater communication systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Adaptive implementation of turbo multi-user detection architecture

MULTI-access techniques have been adopted widely for communications in underwater acoustic channels, which present many challenges to the development of reliable and practical systems. In such an environment, the unpredictable and complex ocean conditions cause the acoustic waves to be affected by many factors such as limited bandwidth, large propagation losses, time variations and long latency, which limit the usefulness of such techniques. Additionally, multiple access interference (MAI) signals and poor estimation of the unknown channel parameters in the presence of limited training sequences are two of the major problems that degrade the performance of such technologies. In this thesis, two different single-element multi-access schemes, interleave division multiple access (IDMA) and code division multiple access (CDMA), employing decision feedback equalization (DFE) and soft Rake-based architectures, are proposed for multi-user underwater communication applications. By using either multiplexing pilots or continuous pilots, these adaptive turbo architectures with carrier phase tracking are jointly optimized based on the minimum mean square error (MMSE) criterion and adapted iteratively by exchanging soft information in terms of Log-Likelihood Ratio (LLR) estimates with the single-user’s channel decoders. The soft-Rake receivers utilize developed channel estimation and the detection is implemented using parallel interference cancellation (PIC) to remove MAI effects between users. These architectures are investigated and applied to simulated data and data obtained from realistic underwater communication trials using off-line processing of signals acquired during sea-trials in the North Sea. The results of different scenarios demonstrate the penalty in performance as the fading induces irreducible error rates that increase with channel delay spread and emphasize the benefits of using coherent direct adaptive receivers in such reverberant channels. The convergence behaviour of the detectors is evaluated using EXIT chart analyses and issues such as the adaptation parameters and their effects on the performance are also investigated. However, in some cases the receivers with partial knowledge of the interleavers’ patterns or codes can still achieve performance comparable to those with full knowledge. Furthermore, the thesis describes implementation issues of these algorithms using digital signal processors (DSPs), such as computational complexity and provides valuable guidelines for the design of real time underwater communication systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo