139,750 research outputs found
A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification
This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC
A 96-Channel FPGA-based Time-to-Digital Converter
We describe an FPGA-based, 96-channel, time-to-digital converter (TDC)
intended for use with the Central Outer Tracker (COT) in the CDF Experiment at
the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC
cards, each serving 96 wires of the chamber. The TDC is physically configured
as a 9U VME card. The functionality is almost entirely programmed in firmware
in two Altera Stratix FPGA's. The special capabilities of this device are the
availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and
abundant memory. The TDC system operates with an input resolution of 1.2 ns.
Each input can accept up to 7 hits per collision. The time-to-digital
conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and
filling a circular memory; the memory addresses of logical transitions (edges)
in the input data are then translated into the time of arrival and width of the
COT pulses. Memory pipelines with a depth of 5.5 s allow deadtime-less
operation in the first-level trigger. The TDC VME interface allows a 64-bit
Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47
Mbytes/sec. The TDC also contains a separately-programmed data path that
produces prompt trigger data every Tevatron crossing. The full TDC design and
multi-card test results are described. The physical simplicity ensures
low-maintenance; the functionality being in firmware allows reprogramming for
other applications.Comment: 32 pages, 13 figure
Recommended from our members
Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Rate augmented digital to analog converter Patent
Development and characteristics of rate augmented digital to analog converter for computed time-dependent dat
Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB
Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in barn owl. The circuit occupies small silicon area, and its direct mapping from time to position-code makes conversion rates up to 500Msps possible. Specialty of the circuit is the structural and functional symmetry. Therefore the role of start and stop signals are interchangeable. In other words negative delay is acceptable: the circuit has no dead time problems. These are benefits of the biology model of the auditory scene representation in the bird's brain. The prototype chip is implemented in 0.35μm CMOS having less than 30ps single-shot resolution in the measurements.Hungarian National Research Foundation TS4085
Digital-voltage curve generator
Curve generator capable of producing precisely repeatable curve for any single-valued function of voltage versus time uses digital approach, implemented by means of clocked feedback shift register, large scale integrated circuit diode matrix comprising about 12,000 diodes, counter, and digital-to-analog converter
Development of a TDC to equip a Liquid Xenon PET prototype
A Time to Digital Converter was designed (CMOS 0.35 $\mum) in order to be
used in Liquid Xenon PET prototype. The circuit proved to be able to work at
-120 degrees C, while showing a resolution of 250 ps. The circuit enables a low
readout dead time (<90 ns) and provides a fully synchronous digital interface
for easy data retrieval.Comment: 4 pages, submitted to IEEE Transactions on Nuclear Scienc
The SAMPIC Waveform and Time to Digital Converter
Sce ElectroniqueInternational audienceSAMPIC is a Waveform and Time to DigitalConverter (WTDC) multichannel chip. Each of its 16 channelsassociates a DLL-based TDC providing a raw time with an ultrafastanalog memory allowing fine timing extraction as well asother parameters of the pulse. Each channel also integrates adiscriminator that can trigger itself independently or participateto a more complex trigger. After triggering, analog data isdigitized by an on-chip ADC and only that corresponding to aregion of interest is sent serially to the DAQ. The association ofthe raw and fine timings permits achieving timing resolutions of afew ps rms. The paper describes the detailed SAMPIC0architecture and reports its main measured performances
- …