A 16-channel Digital TDC Chip with internal buffering and selective readout for the DIRC Cherenkov counter of the BABAR experiment

A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns, the conversion time 32 ns and the full-scale 32 mus. The data driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The time measuring scale is constantly locked to the phase of the (external) clock. The linearity is better than 80 ps rms. The dead time loss is less than 0.1% for incoherent random input at a rate of 100 khz on each channel. At such a rate the power dissipation is less than 100 mw. The die size is 36 mm2.Comment: Latex, 18 pages, 13 figures (14 .eps files), submitted to NIM

A new 130nm F.E readout chip for microstrip detectors

In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future International Linear Collider. The chip includes eighty eight channels of a full analog signal processing chain and analog to digital conversion with the corresponding digital controls and readout channels. The chip is 5x10mm2 where the analog implementation represents 4/5 of the total Silicon area.Comment: 3 pages, 4 figures, LCWS08 worksho

Sex, Drugs, and Reckless Driving: Are Measures Biased Toward Identifying Risk-Taking in Men?

This is the author accepted manuscript. The final version is available from SAGE Publications via the DOI in this record.We investigated whether risk-taking measures inadvertently focus on behaviors that are more normative for men, resulting in the overestimation of gender differences. Using a popular measure of risk-taking (Domain-Specific Risk-Taking) in Study 1 (N = 99), we found that conventionally used behaviors were more normative for men, while, overall, newly developed behaviors were not. In Studies 2 (N = 114) and 3 (N = 124), we demonstrate that differences in normativity are reflected in gender differences in self-reported risk-taking, which are dependent on the specific items used. Study 3 further demonstrates that conventional, masculine risk behaviors are perceived as more risky than newly generated, more feminine items, even when risks are matched. We conclude that there is confirmation bias in risk-taking measurement.The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This work was supported by an internal competitive grant from the Melbourne Business School, University of Melbourne, awarded to Cordelia Fine, who is also grateful for the support of the Women’s Leadership Institute Australia. This work was also supported by an internal competitive grant from the College of Life and Environmental Sciences, University of Exeter, awarded to Thekla Morgenroth and Michelle Ryan. Michelle Ryan was also supported by a British Academy Mid-Career Fellowshi

Silicon Data Acquisition and Front-End Electronics

A highly integrated Front-End readout and Data Acquisition scheme for Silicon trackers is presented. In this context, a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, having in view a highly multiplexed and sparsified readout global strategy. First results are presented

A 96-Channel FPGA-based Time-to-Digital Converter

We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA's. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 $\mu$s allow deadtime-less operation in the first-level trigger. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.Comment: 32 pages, 13 figure

Front-End and Readout Electronics for Silicon Trackers at the ILC

A highly integrated readout scheme for Silicon trackers making use of Deep Sub-Micron CMOS electronics is presented. In this context,a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, each channel comprising a low noise amplifier, a pulse shaper, a sample and hold and a comparator. First results are presented

Evaluierung von annif an der TIB - ein Werkstattbericht

Ein Werkstattbericht aus der TIB über das Toolkit annif

Development of a sampling ASIC for fast detector signals

International audienceIn the context of the Large Area Picosecond Photodetector (LAPPD) pro ject the motivation to measure time-of-flight at the picosecond reso- lution has pushed towards a faster signal rise-time (below 100 ps) and a higher bandwidth output (higher than 1 GHz) detector, thus, leading to a new signal development and integrity studies of Micro-Channel Plates (MCP) photo-detectors. Similarly, the signal path, is being simulated and characterized, from the anodes to the input of the readout electronics, to minimise losses. Furthermore, to acquire the detector fast pulses a new 10 Gs/s high input bandwidth, 130 nm CMOS sampling chip is being de- veloped