B(2): P(M) DUAL RADIX SYSTEMS - THEORY, DESIGN, AND I(SQUARE)L IMPLEMENTATION.

The upward compatibility of binary Boolean algebra with Post algebra was examined. There exists in a Post algebra, P(m), a single two-element Boolean algebra, B(2) {4}. If the complement operation in P(m) is the pseudo-complement or strong negation, then more than one B(2) to P(m) mapping is possible. For m = 2('N), N an integer greater than one, there are 2('N-1) homomorphic mappings of B(2) into P(m). Standard B(2):P(4) building blocks were designed and constructed with integrated injection logic to demonstrate the practical aspects of the dual radix concept. An algorithm for finding the maximum compatible mapping from B(2) to P(m) for completely and incompletely specified functions was developed. Finally, memory elements, bus design, and basic architecture to support a B(2):P(4) processor were considered and comments concerning a B(2) machine operating in a P(m) host were made

Report on the formal specification and partial verification of the VIPER microprocessor

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed

Threshold elements and the design of sequential switching networks

Includes bibliographies."AD 657370."[by] A.K. Susskind, D.R. Haring [and] C.L. Liu

Algorithm for Tant Synthesis and Its Sequential Application

Electrical Engineerin

Techniques for the realization of ultra- reliable spaceborne computer Final report

Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer

Spectral Methods for Boolean and Multiple-Valued Input Logic Functions

Spectral techniques in digital logic design have been known for more than thirty years. They have been used for Boolean function classification, disjoint decomposition, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear pre- and post-filters), multiplexer synthesis, prime implicant extraction by spectral summation, threshold logic synthesis, estimation of logic complexity, testing, and state assignment. This dissertation resolves many important issues concerning the efficient application of spectral methods used in the computer-aided design of digital circuits. The main obstacles in these applications were, up to now, memory requirements for computer systems and lack of the possibility of calculating spectra directly from Boolean equations. By using the algorithms presented here these obstacles have been overcome. Moreover, the methods presented in this dissertation can be regarded as representatives of a whole family of methods and the approach presented can be easily adapted to other orthogonal transforms used in digital logic design. Algorithms are shown for Adding, Arithmetic, and Reed-Muller transforms. However, the main focus of this dissertation is on the efficient computer calculation of Rademacher-Walsh spectra of Boolean functions, since this particular ordering of Walsh transforms is most frequently used in digital logic design. A theory has been developed to calculate the Rademacher-Walsh transform from a cube array specification of incompletely specified Boolean functions. The importance of representing Boolean functions as arrays of disjoint ON- and DC- cubes has been pointed out, and an efficient new algorithm to generate disjoint cubes from non-disjoint ones has been designed. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. By such an approach each spectral coefficient can be calculated separately or all the coefficients can be calculated in parallel. These advantages are absent in the existing methods. The possibility of calculating only some coefficients is very important since there are many spectral methods in digital logic design for which the values of only a few selected coefficients are needed. Most of the current methods used in the spectral domain deal only with completely specified Boolean functions. On the other hand, all of the algorithms introduced here are valid, not only for completely specified Boolean functions, but for functions with don\u27t cares. Don\u27t care minterms are simply represented in the form of disjoint cubes. The links between spectral and classical methods used for designing digital circuits are described. The real meaning of spectral coefficients from Walsh and other orthogonal spectra in classical logic terms is shown. The relations presented here can be used for the calculation of different transforms. The methods are based on direct manipulations on Karnaugh maps. The conversion start with Karnaugh maps and generate the spectral coefficients. The spectral representation of multiple-valued input binary functions is proposed here for the first time. Such a representation is composed of a vector of Walsh transforms each vector is defined for one pair of the input variables of the function. The new representation has the advantage of being real-valued, thus having an easy interpretation. Since two types of codings of values of binary functions are used, two different spectra are introduced. The meaning of each spectral coefficient in classical logic terms is discussed. The mathematical relationships between the number of true, false, and don\u27t care minterms and spectral coefficients are stated. These relationships can be used to calculate the spectral coefficients directly from the graphical representations of binary functions. Similarly to the spectral methods in classical logic design, the new spectral representation of binary functions can find applications in many problems of analysis, synthesis, and testing of circuits described by such functions. A new algorithm is shown that converts the disjoint cube representation of Boolean functions into fixed-polarity Generalized Reed-Muller Expansions (GRME). Since the known fast algorithm that generates the GRME, based on the factorization of the Reed-Muller transform matrix, always starts from the truth table (minterms) of a Boolean function, then the described method has advantages due to a smaller required computer memory. Moreover, for Boolean functions, described by only a few disjoint cubes, the method is much more efficient than the fast algorithm. By investigating a family of elementary second order matrices, new transforms of real vectors are introduced. When used for Boolean function transformations, these transforms are one-to-one mappings in a binary or ternary vector space. The concept of different polarities of the Arithmetic and Adding transforms has been introduced. New operations on matrices: horizontal, vertical, and vertical-horizontal joints (concatenations) are introduced. All previously known transforms, and those introduced in this dissertation can be characterized by two features: ordering and polarity . When a transform exists for all possible polarities then it is said to be generalized . For all of the transforms discussed, procedures are given for generalizing and defining for different orderings. The meaning of each spectral coefficient for a given transform is also presented in terms of standard logic gates. There exist six commonly used orderings of Walsh transforms: Hadamard, Rademacher, Kaczmarz, Paley, Cal-Sal, and X. By investigating the ways in which these known orderings are generated the author noticed that the same operations can be used to create some new orderings. The generation of two new Walsh transforms in Gray code orderings, from the straight binary code is shown. A recursive algorithm for the Gray code ordered Walsh transform is based on the new operator introduced in this presentation under the name of the bi-symmetrical pseudo Kronecker product . The recursive algorithm is the basis for the flow diagram of a constant geometry fast Walsh transform in Gray code ordering. The algorithm is fast (N 10g2N additions/subtractions), computer efficient, and is implemente

Principles of logic design

This study involves logic design and switching theory, in particular their practical application to the logic design and understanding of digital machines. Digital machines, of course, play an extremely important role in that large class of machines known as digital computers. But they also play an important role in many other kinds of practical devices important in the design of communications systems, digital control systems, counters, registers, digital meters, and so on. The basic content of switching theory is very simple. It embodies that body of machines and machine behavior that can be realized with "switches", things that are either "on" or "off", and nothing, really, could be much simpler than that. Of course the world is really comprised of very many complex structures which are really composed of exceedingly simple lesser structures, so that we really shouldn't be too surprised that even though the elements of switching theory are quite simple, their consequences are not necessarily so. The goals of our study are several, and include at least the following: 1) to develop some understanding and capability in using the techniques, design procedures, and models that have been developed for understanding and designing digital networks; 2) to explore in some modest detail the kinds of questions with which logic designers and practitioners concern themselves; 3) to develop an appreciation for the tremendous variation possible in digital design requirements and specifications, i. e,, for the complexity of the 'finite' digital problem, and hence an understanding of the need for systematic design techniques by which to attack such problems; 4) to gain some practice with the fundamental tools and techniques of logic design I so that the reader can adapt the techniques to the "new" problem presented by his own particular design constraints; and 5) to provide an introduction to the literature so that the discerning student can, in the future, dip into the ever growing literature in the field, and find it to some degree comprehensible, and advantageous to use

On-line diagnosis of sequential systems, 2

The theory and techniques applicable to the on-line diagnosis of sequential systems, were investigated. A complete model for the study of on-line diagnosis is developed. First an appropriate class of system models is formulated which can serve as a basis for a theoretical study of on-line diagnosis. Then notions of realization, fault, fault-tolerance and diagnosability are formalized which have meaningful interpretations in the the context of on-line diagnosis. The diagnosis of systems which are structurally decomposed and are represented as a network of smaller systems is studied. The fault set considered is the set of faults which only affect one component system is the network. A characterization of those networks which can be diagnosed using a purely combinational detector is achieved. A technique is given which can be used to realize any network by a network which is diagnosable in the above sense. Limits are found on the amount of redundancy involved in any such technique

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design