In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed

A simple mathematical theory for Simple Volatile Memristors and their spiking circuits

In pursuit of neuromorphic (brain-inspired) devices, memristors (memory-resistors) have emerged as promising candidates for emulating neuronal circuitry. Here we mathematically define a class of Simple Volatile Memristors (SVMs), which notably includes various fluidic iontronic devices that have recently garnered significant interest due to their unique quality of operating within the same medium as the brain. We show that symmetric SVMs produce non self-crossing current-voltage hysteresis loops, while simple asymmetric SVMs produce self-crossing loops. Additionally, we derive a general expression for the enclosed area in a loop, providing a relation between the voltage frequency and the SVM memory timescale. These general results are shown to materialise in physical finite-element calculations of microfluidic memristors. An SVM-based circuit has been proposed that exhibits all-or-none and tonic neuronal spiking. We generalise and analyse this spiking circuit, characterising it as a two-dimensional dynamical system. Additionally, we demonstrate that stochastic effects can induce novel neuronal firing modes absent in the deterministic case. Through our analysis, the circuit dynamics are well understood, while retaining its explicit link with the physically plausible underlying system

From memory to processing : a reaction-diffusion approach to neuromorphic computing

The goal of this research is to bridge the gap between the physiological brain and mathematically based neuromorphic computing models. As such, the reaction-diffusion method was chosen as it can naturally exhibit properties like propagation of excitation that are seen in the brain, but not current neuromorphic computing models. A reaction-diffusion memory unit was created to demonstrate the key memory functions of sensitization, habituation, and dishabituation, while a reaction-diffusion brain module was established to perform the specific processing task of single-digit binary addition. The results from both approaches were consistent with existing literature detailing physiological memory and processing in the human brain

Bio-inspired learning and hardware acceleration with emerging memories

Machine Learning has permeated many aspects of engineering, ranging from the Internet of Things (IoT) applications to big data analytics. While computing resources available to implement these algorithms have become more powerful, both in terms of the complexity of problems that can be solved and the overall computing speed, the huge energy costs involved remains a significant challenge. The human brain, which has evolved over millions of years, is widely accepted as the most efficient control and cognitive processing platform. Neuro-biological studies have established that information processing in the human brain relies on impulse like signals emitted by neurons called action potentials. Motivated by these facts, the Spiking Neural Networks (SNNs), which are a bio-plausible version of neural networks have been proposed as an alternative computing paradigm where the timing of spikes generated by artificial neurons is central to its learning and inference capabilities. This dissertation demonstrates the computational power of the SNNs using conventional CMOS and emerging nanoscale hardware platforms. The first half of this dissertation presents an SNN architecture which is trained using a supervised spike-based learning algorithm for the handwritten digit classification problem. This network achieves an accuracy of 98.17% on the MNIST test data-set, with about 4X fewer parameters compared to the state-of-the-art neural networks achieving over 99% accuracy. In addition, a scheme for parallelizing and speeding up the SNN simulation on a GPU platform is presented. The second half of this dissertation presents an optimal hardware design for accelerating SNN inference and training with SRAM (Static Random Access Memory) and nanoscale non-volatile memory (NVM) crossbar arrays. Three prominent NVM devices are studied for realizing hardware accelerators for SNNs: Phase Change Memory (PCM), Spin Transfer Torque RAM (STT-RAM) and Resistive RAM (RRAM). The analysis shows that a spike-based inference engine with crossbar arrays of STT-RAM bit-cells is 2X and 5X more efficient compared to PCM and RRAM memories, respectively. Furthermore, the STT-RAM design has nearly 6X higher throughput per unit Watt per unit area than that of an equivalent SRAM-based (Static Random Access Memory) design. A hardware accelerator with on-chip learning on an STT-RAM memory array is also designed, requiring $16$ bits of floating-point synaptic weight precision to reach the baseline SNN algorithmic performance on the MNIST dataset. The complete design with STT-RAM crossbar array achieves nearly 20X higher throughput per unit Watt per unit mm^2 than an equivalent design with SRAM memory. In summary, this work demonstrates the potential of spike-based neuromorphic computing algorithms and its efficient realization in hardware based on conventional CMOS as well as emerging technologies. The schemes presented here can be further extended to design spike-based systems that can be ubiquitously deployed for energy and memory constrained edge computing applications

Energy Efficient and Error Resilient Neuromorphic Computing in VLSI

Realization of the conventional Von Neumann architecture faces increasing challenges due to growing process variations, device reliability and power consumption. As an appealing architectural solution, brain-inspired neuromorphic computing has drawn a great deal of research interest due to its potential improved scalability and power efficiency, and better suitability in processing complex tasks. Moreover, inherit error resilience in neuromorphic computing allows remarkable power and energy savings by exploiting approximate computing. This dissertation focuses on a scalable and energy efficient neurocomputing architecture which leverages emerging memristor nanodevices and a novel approximate arithmetic for cognitive computing. First, brain-inspired digital neuromorphic processor (DNP) architecture with memristive synaptic crossbar is presented for large scale spiking neural networks. We leverage memristor nanodevices to build an N ×N crossbar array to store not only multibit synaptic weight values but also the network configuration data with significantly reduced area cost. Additionally, the crossbar array is accessible both column- and row-wise to significantly expedite the synaptic weight update process for on-chip learning. The proposed digital pulse width modulator (PWM) readily creates a binary pulse with various durations to read and write the multilevel memristors with low cost. Our design integrates N digital leaky integrate-and-fire (LIF) silicon neurons to mimic their biological counterparts and the respective on-chip learning circuits for implementing spike timing dependent plasticity (STDP) learning rules. The proposed column based analog-to-digital conversion (ADC) scheme accumulates the pre-synaptic weights of a neuron efficiently and reduces silicon area by using only one shared arithmetic unit for processing LIF operations of all N neurons. With 256 silicon neurons, the learning circuits and 64K synapses, the power dissipation and area of our design are evaluated as 6.45 mW and 1.86 mm2, respectively, in a 90 nm CMOS technology. Furthermore, arithmetic computations contribute significantly to the overall processing time and power of the proposed architecture. In particular, addition and comparison operations represent 88.5% and 42.9% of processing time and power for digital LIF computation, respectively. Hence, by exploiting the built-in resilience of the presented neuromorphic architecture, we propose novel approximate adder and comparator designs to significantly reduce energy consumption with a very low er- ror rate. The significantly improved error rate and critical path delay stem from a novel carry prediction technique that leverages the information from less significant input bits in a parallel manner. An error magnitude reduction scheme is proposed to further reduce amount of error once detected with low cost in the proposed adder design. Implemented in a commercial 90 nm CMOS process, it is shown that the proposed adder is up to 2.4× faster and 43% more energy efficient over traditional adders while having an error rate of only 0.18%. Additionally, the proposed com- parator achieves an error rate of less than 0.1% and an energy reduction of up to 4.9× compared to the conventional ones. The proposed arithmetic has been adopted in a VLSI-based neuromorphic character recognition chip using unsupervised learning. The approximation errors of the proposed arithmetic units have been shown to have negligible impacts on the training process. Moreover, the energy saving of up to 66.5% over traditional arithmetic units is achieved for the neuromorphic chip with scaled supply levels

Towards energy-efficient hardware acceleration of memory-intensive event-driven kernels on a synchronous neuromorphic substrate

Spiking neural networks are increasingly becoming popular as low-power alternatives to deep learning architectures. To make edge processing possible in resource-constrained embedded devices, there is a requirement for reconfigurable neuromorphic accelerators that can cater to various topologies and neural dynamics typical to these networks. Subsequently, they also must consolidate energy consumption in emulating these dynamics. Since spike processing is essentially memory-intensive in nature, a significant proportion of the system\u27s power consumption can be reduced by eliminating redundant memory traffic to off-chip storage that holds the large synaptic data for the network. In this work, I will present CyNAPSE, a digital neuromorphic acceleration fabric that can emulate different types of spiking neurons and network topologies for efficient inference. The accelerator is functionally verified on a set of benchmarks that vary significantly in topology and activity while solving the same underlying task. By studying the memory access patterns, locality of data and spiking activity, we establish the core factors that limit conventional cache replacement policies from performing well. Accordingly, a domain-specific memory management scheme is proposed which exploits the particular use-case to attain visibility of future data-accesses in the event-driven simulation framework. To make it even more robust to variations in network topology and activity of the benchmark, we further propose static and dynamic network-specific enhancements to adaptively equip the scheme with more insight. The strategy is explored and evaluated with the set of benchmarks using a software simulation of the accelerator and an in-house cache simulator. In comparison to conventional policies, we observe up to 23% more reduction in net power consumption

Architectures and Design of VLSI Machine Learning Systems

Quintillions of bytes of data are generated every day in this era of big data. Machine learning techniques are utilized to perform predictive analysis on these data, to reveal hidden relationships and dependencies and perform predictions of outcomes and behaviors. The obtained predictive models are used to interpret the existing data and predict new data information. Nowadays, most machine learning algorithms are realized by software programs running on general-purpose processors, which usually takes a huge amount of CPU time and introduces unbelievably high energy consumption. In comparison, a dedicated hardware design is usually much more efficient than software programs running on general-purpose processors in terms of runtime and energy consumption. Therefore, the objective of this dissertation is to develop efficient hardware architectures for mainstream machine learning algorithms, to provide a promising solution to addressing the runtime and energy bottlenecks of machine learning applications. However, it is a really challenging task to map complex machine learning algorithms to efficient hardware architectures. In fact, many important design decisions need to be made during the hardware development for efficient tradeoffs. In this dissertation, a parallel digital VLSI architecture for combined SVM training and classification is proposed. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The parallel SVM processors provide a significant training time speedup and energy reduction compared with the software SVM algorithm running on a general-purpose CPU. Furthermore, a liquid state machine based neuromorphic learning processor with integrated training and recognition is proposed. A novel theoretical measure of computational power is proposed to facilitate fast design space exploration of the recurrent reservoir. Three low-power techniques are proposed to improve the energy efficiency. Meanwhile, a 2-layer spiking neural network with global inhibition is realized on Silicon. In addition, we also present architectural design exploration of a brain-inspired digital neuromorphic processor architecture with memristive synaptic crossbar array, and highlight several synaptic memory access styles. Various analog-to-digital converter schemes have been investigated to provide new insights into the tradeoff between the hardware cost and energy consumption

Neuromorphic nanophotonic systems for artificial intelligence

Over the last decade, we have witnessed an astonishing pace of development in the field of artificial intelligence (AI), followed by proliferation of AI algorithms into virtually every domain of our society. While modern AI models boast impressive performance, they also require massive amounts of energy and resources for operation. This is further fuelling the research into AI-specific, optimised computing hardware. At the same time, the remarkable energy efficiency of the brain brings an interesting question: Can we further borrow from the working principles of biological intelligence to realise a more efficient artificial intelligence? This can be considered as the main research question in the field of neuromorphic engineering. Thanks to the developments in AI and recent advancements in the field of photonics and photonic integration, research into light-powered implementations of neuromorphic hardware has recently experienced a significant uptick of interest. In such hardware, the aim is to seize some of the highly desirable properties of photonics not just for communication, but also to perform computation. Neurons in the brain frequently process information (compute) and communicate using action potentials, which are brief voltage spikes that encode information in the temporal domain. Similar dynamical behaviour can be elicited in some photonic devices, at speeds multiple orders of magnitude higher. Such devices with the capability of neuron-like spiking are of significant research interest for the field of neuromorphic photonics. Two distinct types of such excitable, spiking systems operating with optical signals are studied and investigated in this thesis. First, a vertical cavity surface emitting laser (VCSEL) can be operated under a specific set of conditions to realise a high-speed, all-optical excitable photonic neuron that operates at standard telecom wavelengths. The photonic VCSEL-neuron was dynamically characterised and various information encoding mechanisms were studied in this device. In particular, a spiking rate-coding regime of operation was experimentally demonstrated, and its viability for performing spiking domain conversion of digital images was explored. Furthermore, for the first time, a joint architecture utilising a VCSEL-neuron coupled to a photonic integrated circuit (PIC) silicon microring weight bank was experimentally demonstrated in two different functional layouts. Second, an optoelectronic (O/E/O) circuit based upon a resonant tunnelling diode (RTD) was introduced. Two different types of RTD devices were studied experimentally: a higher output power, µ-scale RTD that was RF coupled to an active photodetector and a VCSEL (this layout is referred to as a PRL node); and a simplified, photosensitive RTD with nanoscale injector that was RF coupled to a VCSEL (referred to as a nanopRL node). Hallmark excitable behaviours were studied in both devices, including excitability thresholding and refractory periods. Furthermore, a more exotic resonate and-fire dynamical behaviour was also reported in the nano-pRL device. Finally, a modular numerical model of the RTD was introduced, and various information processing methods were demonstrated using both a single RTD spiking node, as well as a perceptron-type spiking neural network with physical models of optoelectronic RTD nodes serving as artificial spiking neurons.Over the last decade, we have witnessed an astonishing pace of development in the field of artificial intelligence (AI), followed by proliferation of AI algorithms into virtually every domain of our society. While modern AI models boast impressive performance, they also require massive amounts of energy and resources for operation. This is further fuelling the research into AI-specific, optimised computing hardware. At the same time, the remarkable energy efficiency of the brain brings an interesting question: Can we further borrow from the working principles of biological intelligence to realise a more efficient artificial intelligence? This can be considered as the main research question in the field of neuromorphic engineering. Thanks to the developments in AI and recent advancements in the field of photonics and photonic integration, research into light-powered implementations of neuromorphic hardware has recently experienced a significant uptick of interest. In such hardware, the aim is to seize some of the highly desirable properties of photonics not just for communication, but also to perform computation. Neurons in the brain frequently process information (compute) and communicate using action potentials, which are brief voltage spikes that encode information in the temporal domain. Similar dynamical behaviour can be elicited in some photonic devices, at speeds multiple orders of magnitude higher. Such devices with the capability of neuron-like spiking are of significant research interest for the field of neuromorphic photonics. Two distinct types of such excitable, spiking systems operating with optical signals are studied and investigated in this thesis. First, a vertical cavity surface emitting laser (VCSEL) can be operated under a specific set of conditions to realise a high-speed, all-optical excitable photonic neuron that operates at standard telecom wavelengths. The photonic VCSEL-neuron was dynamically characterised and various information encoding mechanisms were studied in this device. In particular, a spiking rate-coding regime of operation was experimentally demonstrated, and its viability for performing spiking domain conversion of digital images was explored. Furthermore, for the first time, a joint architecture utilising a VCSEL-neuron coupled to a photonic integrated circuit (PIC) silicon microring weight bank was experimentally demonstrated in two different functional layouts. Second, an optoelectronic (O/E/O) circuit based upon a resonant tunnelling diode (RTD) was introduced. Two different types of RTD devices were studied experimentally: a higher output power, µ-scale RTD that was RF coupled to an active photodetector and a VCSEL (this layout is referred to as a PRL node); and a simplified, photosensitive RTD with nanoscale injector that was RF coupled to a VCSEL (referred to as a nanopRL node). Hallmark excitable behaviours were studied in both devices, including excitability thresholding and refractory periods. Furthermore, a more exotic resonate and-fire dynamical behaviour was also reported in the nano-pRL device. Finally, a modular numerical model of the RTD was introduced, and various information processing methods were demonstrated using both a single RTD spiking node, as well as a perceptron-type spiking neural network with physical models of optoelectronic RTD nodes serving as artificial spiking neurons