Low frequency Quadrature detector design, simulation and implementation for use in underground communication

The earth does not easily propagate high frequency signals. Low frequency, through the earth, signals would provide better penetration of the earth surface. Extremely low frequency communications has been a challenge for many years because of the underlying limitations such as significant background noise, and large antenna size. This thesis investigates the design of a compact quadrature sampling detector for extremely low frequency through the earth communication. It is hoped that a receiver such as that designed herein could receive signals at frequencies much much less than 10 kHz through the earth. Furthermore, this thesis compares the method of quadrature reception at these extremely low frequencies using simulation and hardware implementation with higher frequencies. This thesis also discusses the design of quadrature sampling detector and performance measurement of the quadrature detector at these extremely low frequencies. The results of the quadrature detection hardware testing show that it is indeed possible to use a quadrature detector at such low frequencies

8-Phase Ring oscillator for modern receivers

The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers

DEVELOPMENT OF AN UWB RADAR SYSTEM

An ultra-wideband radar system is built at the University of Tennessee with the goal to develop a ground penetrating radar (GPR). The radar is required to transmit and receive a very narrow pulse signal in the time domain. The bistatic radar transmits a pulse through an ultrawide spiral antenna and receives the pulse by a similar antenna. Direct sampling is used to improve the performance of the impulse radar allowing up to 1.5 GHz of bandwidth to be used for signal processing and target detection with high resolution. Using direct sampling offers a less complex system design than traditional lower sample rate, super-heterodyne systems using continuous wave or step frequency methods while offering faster results than conventional equivalent time sampling techniques that require multiple data sets and significant post-processing. These two points are particularly important for a system that may be used in the field in potentially dangerous environments. Direct sampling radar systems, while still frequency limited, are continually improving their upper frequencies boundaries due to more power efficient, higher sampling rate analog to digital converters (ADCs) which relates directly to better subsurface resolution for potential target detection

Measuring Receiver Benchmark for Conducted and Radiated Emissions Testing in Space Applications

This paper compares the measurement results obtained from three different implementations of measuring receivers regarding spectral level accuracy. The objective is to validate the suitability of direct sampling electromagnetic emissions measurements with respect to those delivered by a high-end EMI receiver in frequency swept and FFT modes. The experimental setups follow the verification methods described in the ECSS-E-ST-20-07C Rev.2 standard to set realistic and reproducible conditions. Between 50 kHz and 100 MHz, common mode and differential mode currents are measured when multisine excitation signals with controlled amplitude profiles are used as references. Subsequently, conducted and radiated emissions tests are run to investigate the correlation between measurements with the different receivers. The instruments used are a low-cost USB digitiser Picoscope PS5444D, a high-performance benchtop oscilloscope R&S RTO6 and the R&S ESW44 full-compliant EMI test receiver. The analysis concludes that the emissions measurements performed with the direct sampling approach are excellent for the intended application, exhibiting an accuracy comparable to the dedicated EMI test receiver and a well adequate dynamic range and noise level.The project (21NRM06 EMC-STD) has received funding from the European Partnership on Metrology, co-financed by the European Union's Horizon Europe Research and Innovation Programme and by the Participating States. EMC Barcelona's project under grant number SNEO-20211223 has received funding from CDTI, which is supported by "Ministerio de Ciencia e Innovación" and financed by the European Union - NextGenerationEU - through the guidelines included in the `Plan de Recuperación, Transformación y Resiliencia". Dr. Azpúrua has received funding from the StandICT.eu 2023 project, financed by the European Union's Horizon Europe - Research and Innovation Programme - under grant agreement No. 951972. Dr. Pous' work was supported in part by the European Union's Horizon 2020 research and innovation programme under Marie Skłodowska-Curie grant agreement No. 801342 (TecniospringINDUSTRY) and the Government of Catalonia's Agency for Business Competitiveness (ACCIÓ) and in part by the Spanish "Ministerio de Ciencia e Innovaci´on" under project PID2019-106120RBC31/AEI/10.13039/501100011033

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers

Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user equipments have created a demand for low-cost, low-power and low-area devices with tight specifications imposed by standards. The advances in CMOS technology allows, nowadays, designers to implement circuits that work at high-frequencies, thus, allowing the complete implementation of RF front ends in a single chip. In this work, a co-design strategy for the implementation of a fully integrated CMOS receiver for use in the ISM band is presented. The main focus is given to the Mixer and the ADC blocks of the presented architecture. The traditional approach used in RF design requires 50 matching buffers and networks and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign strategy avoids the use of DC choke inductors for Mixer biasing, because it is possible to use the DC level from the output of the LNA and the LO to provide bias to the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs are transistors gates, we should consider voltage instead of power and avoid the 50 matching networks. The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to achieve low-power and high sampling frequency. To meet these goals, parametric amplification based on MOS varactors is applied to reduce the offset voltage of the comparators, avoiding the traditional and power-consuming approach of active pre-amplification gain stages