190 research outputs found
Design of adaptive analog filters for magnetic front-end read channels
Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de
muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem
para canais de leitura em sistemas de gravação e reprodução de dados em suporte
magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a
1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste
trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços
muito significativos a nível mundial com o objectivo de se investigarem novas técnicas
de realização de filtros em circuito integrado monolítico, especialmente em tecnologia
CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo
a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização
de soluções com as características desejadas.
Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão
de sinal bem como a escolha de bons modelos matemáticos para o tratamento da
informação e a minimização de erro inerente às aproximações na conformidade aos princípios
físicos dos dispositivos caracterizados.
O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do
canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de
filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado
sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte
magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo,
baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia
digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization)
com base na igualização de sinal utilizando filtros integrados analógicos em tempo
contínuo.
Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação
de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que
a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros
adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo,
dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa
e análise de estruturas ideais no projecto de filtros recorrendo a representações no
espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de
circuitos de transcondutância para a implementação de filtros integrados analógicos em
tempo contínuo.
Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros
no espaço de estados, correspondentes a duas soluções alternativas para a realização de
um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem,
para utilização num canal de leitura de dados em suporte magnético.
Como parte constituinte destes filtros, apresenta-se uma técnica de realização de
circuitos de transcondutância, e de realização de condensadores lineares usando matrizes
de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada
em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se
métodos de adaptação automática capazes de compensar os erros face aos valores nominais
dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os
quais apresentamos os resultados de simulação e de medição experimental obtidos.
Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível
de constituir uma solução para o controlo de posicionamento da cabeça de leitura
em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto
é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância
e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo
de igualação do canal de leitura.
Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de
controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em
Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa
utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency
filters. The motivation of this work was the search for filtering solutions for the readchannel
in recording and reproduction of data on magnetic media systems, with costs and
consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than
the available circuits. Accordingly, as was done in this work, the rapid development of
microelectronics technology raised very significant efforts worldwide in order to investigate
new techniques for implementing such filters in monolithic integrated circuit, especially
in CMOS technology (Complementary Metal Oxide Semiconductor). We present
a comparative study on different hierarchical levels of the project, which led to the realization
and characterization of solutions with the desired characteristics.
In the first level, this study addresses the conceptual question of recording and
transmission of signal and the choice of good mathematical models for the processing of
information and minimization of error inherent in the approaches and in accordance with
the principles of the characterized physical devices.
The main work of this thesis is focused on the hierarchical levels of the architecture
of the read channel and the integrated circuit implementation of its main block - the filtering
block. At the architecture level of the read channel this work presents a comprehensive
study on existing methodologies of adaptation and signal recovery of data on
magnetic media. This project appears in the sequence of the proposed solution for a lowcost,
low consumption, low voltage, low complexity, using CMOS digital technology for
the performance of a DFE (Decision Feedback Equalization) based on the equalization of
the signal using integrated analog filters in continuous time.
At the project level of implementation of the filtering block and techniques for implementing
filters and its building components, it was concluded that the technique based
on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate
for the implementation of very-high-frequency adaptive filters. We defined in
this lower level, two sub-levels of depth study for this thesis, namely: research and analysis
of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation
of continuous time integrated analog filters.
Following this study, we present and compare two filtering structures operating in
the space of states, corresponding to two alternatives for achieving a realization of an
adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a
read-channel for magnetic media devices.
As a constituent part of these filters, we present a technique for the realization of
transconductance circuits and for the implementation of linear capacitors using arrays of
MOSFET transistors for signal processing in very-high-frequency integrated circuits using
sub-micrometric CMOS technology. We present methods capable of automatic adjustment
and compensation for deviation errors in respect to the nominal values of the
components inherent to the tolerances of the fabrication process, for which we present
the simulation and experimental measurement results obtained.
Also as a result of this study, is the presentation of a circuit that provides a solution
for the control of the head positioning on recording/playback systems of data on magnetic
media. The proposed block is an adaptive first-order filter, based on the same transconductance
circuits and equalization techniques proposed and used in the implementation
of the adaptive filter for the equalization of the read channel.
This filter was designed and included in an integrated circuit (Jaguar) used to control
the positioning of the read-head done for ATMEL company in Colorado Springs, and
part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company
Enhanced coding, clock recovery and detection for a magnetic credit card
Merged with duplicate record 10026.1/2299 on 03.04.2017 by CS (TIS)This thesis describes the background, investigation and construction of a system
for storing data on the magnetic stripe of a standard three-inch plastic credit
in: inch card. Investigation shows that the information storage limit within a 3.375 in
by 0.11 in rectangle of the stripe is bounded to about 20 kBytes. Practical issues
limit the data storage to around 300 Bytes with a low raw error rate: a four-fold
density increase over the standard. Removal of the timing jitter (that is prob-'
ably caused by the magnetic medium particle size) would increase the limit to
1500 Bytes with no other system changes. This is enough capacity for either a
small digital passport photograph or a digitized signature: making it possible
to remove printed versions from the surface of the card.
To achieve even these modest gains has required the development of a new
variable rate code that is more resilient to timing errors than other codes in its
efficiency class. The tabulation of the effects of timing errors required the construction
of a new code metric and self-recovering decoders. In addition, a new
method of timing recovery, based on the signal 'snatches' has been invented to
increase the rapidity with which a Bayesian decoder can track the changing velocity
of a hand-swiped card. The timing recovery and Bayesian detector have
been integrated into one computation (software) unit that is self-contained and
can decode a general class of (d, k) constrained codes. Additionally, the unit has
a signal truncation mechanism to alleviate some of the effects of non-linear distortion
that are present when a magnetic card is read with a magneto-resistive
magnetic sensor that has been driven beyond its bias magnetization.
While the storage density is low and the total storage capacity is meagre in
comparison with contemporary storage devices, the high density card may still
have a niche role to play in society. Nevertheless, in the face of the Smart card its
long term outlook is uncertain. However, several areas of coding and detection
under short-duration extreme conditions have brought new decoding methods
to light. The scope of these methods is not limited just to the credit card
An Optimal Unequal Error Protection LDPC Coded Recording System
For efficient modulation and error control coding, the deliberate flipping
approach imposes the run-length-limited(RLL) constraint by bit error before
recording. From the read side, a high coding rate limits the correcting
capability of RLL bit error. In this paper, we study the low-density
parity-check (LDPC) coding for RLL constrained recording system based on the
Unequal Error Protection (UEP) coding scheme design. The UEP capability of
irregular LDPC codes is used for recovering flipped bits. We provide an
allocation technique to limit the occurrence of flipped bits on the bit with
robust correction capability. In addition, we consider the signal labeling
design to decrease the number of nearest neighbors to enhance the robust bit.
We also apply the density evolution technique to the proposed system for
evaluating the code performances. In addition, we utilize the EXIT
characteristic to reveal the decoding behavior of the recommended code
distribution. Finally, the optimization approach for the best distribution is
proven by differential evolution for the proposed system.Comment: 20 pages, 18 figure
CHANNEL CODING TECHNIQUES FOR A MULTIPLE TRACK DIGITAL MAGNETIC RECORDING SYSTEM
In magnetic recording greater area) bit packing densities are achieved through increasing
track density by reducing space between and width of the recording tracks, and/or
reducing the wavelength of the recorded information. This leads to the requirement of
higher precision tape transport mechanisms and dedicated coding circuitry.
A TMS320 10 digital signal processor is applied to a standard low-cost, low precision,
multiple-track, compact cassette tape recording system. Advanced signal processing and
coding techniques are employed to maximise recording density and to compensate for
the mechanical deficiencies of this system. Parallel software encoding/decoding
algorithms have been developed for several Run-Length Limited modulation codes. The
results for a peak detection system show that Bi-Phase L code can be reliably employed
up to a data rate of 5kbits/second/track. Development of a second system employing a
TMS32025 and sampling detection permitted the utilisation of adaptive equalisation to
slim the readback pulse. Application of conventional read equalisation techniques, that
oppose inter-symbol interference, resulted in a 30% increase in performance.
Further investigation shows that greater linear recording densities can be achieved by
employing Partial Response signalling and Maximum Likelihood Detection. Partial
response signalling schemes use controlled inter-symbol interference to increase
recording density at the expense of a multi-level read back waveform which results in an
increased noise penalty. Maximum Likelihood Sequence detection employs soft
decisions on the readback waveform to recover this loss. The associated modulation
coding techniques required for optimised operation of such a system are discussed.
Two-dimensional run-length-limited (d, ky) modulation codes provide a further means of
increasing storage capacity in multi-track recording systems. For example the code rate
of a single track run length-limited code with constraints (1, 3), such as Miller code, can
be increased by over 25% when using a 4-track two-dimensional code with the same d
constraint and with the k constraint satisfied across a number of parallel channels. The k
constraint along an individual track, kx, can be increased without loss of clock
synchronisation since the clocking information derived by frequent signal transitions
can be sub-divided across a number of, y, parallel tracks in terms of a ky constraint. This
permits more code words to be generated for a given (d, k) constraint in two dimensions
than is possible in one dimension. This coding technique is furthered by development of
a reverse enumeration scheme based on the trellis description of the (d, ky) constraints.
The application of a two-dimensional code to a high linear density system employing
extended class IV partial response signalling and maximum likelihood detection is
proposed. Finally, additional coding constraints to improve spectral response and error
performance are discussed.Hewlett Packard, Computer Peripherals Division (Bristol
CROSSTALK-RESILIANT CODING FOR HIGH DENSITY DIGITAL RECORDING
Increasing the track density in magnetic systems is very difficult due to inter-track interference
(ITI) caused by the magnetic field of adjacent tracks. This work presents a
two-track partial response class 4 magnetic channel with linear and symmetrical ITI; and
explores modulation codes, signal processing methods and error correction codes in order
to mitigate the effects of ITI.
Recording codes were investigated, and a new class of two-dimensional run-length
limited recording codes is described. The new class of codes controls the type of ITI
and has been found to be about 10% more resilient to ITI compared to conventional
run-length limited codes. A new adaptive trellis has also been described that adaptively
solves for the effect of ITI. This has been found to give gains up to 5dB in signal to noise
ratio (SNR) at 40% ITI. It was also found that the new class of codes were about 10%
more resilient to ITI compared to conventional recording codes when decoded with the
new trellis.
Error correction coding methods were applied, and the use of Low Density Parity
Check (LDPC) codes was investigated. It was found that at high SNR, conventional
codes could perform as well as the new modulation codes in a combined modulation and
error correction coding scheme. Results suggest that high rate LDPC codes can mitigate
the effect of ITI, however the decoders have convergence problems beyond 30% ITI
Applications of iterative decoding to magnetic recording channels.
Finally, Q-ary LDPC (Q-LDPC) codes are considered for MRCs. Belief propagation decoding for binary LDPC codes is extended to Q-LDPC codes and a reduced-complexity decoding algorithm for Q-LDPC codes is developed. Q-LDPC coded systems perform very well with random noise as well as with burst erasures. Simulations show that Q-LDPC systems outperform RS systems.Secondly, binary low-density parity-check (LDPC) codes are proposed for MRCs. Random binary LDPC codes, finite-geometry LDPC codes and irregular LDPC codes are considered. With belief propagation decoding, LDPC systems are shown to have superior performance over current Reed-Solomon (RS) systems at the range possible for computer simulation. The issue of RS-LDPC concatenation is also addressed.Three coding schemes are investigated for magnetic recording systems. Firstly, block turbo codes, including product codes and parallel block turbo codes, are considered on MRCs. Product codes with other types of component codes are briefly discussed.Magnetic recoding channels (MRCs) are subject to noise contamination and error-correcting codes (ECCs) are used to keep the integrity of the data. Conventionally, hard decoding of the ECCs is performed. In this dissertation, systems using soft iterative decoding techniques are presented and their improved performance is established
EQUALISATION TECHNIQUES FOR MULTI-LEVEL DIGITAL MAGNETIC RECORDING
A large amount of research has been put into areas of signal processing, medium design,
head and servo-mechanism design and coding for conventional longitudinal as well
as perpendicular magnetic recording. This work presents some further investigation in the
signal processing and coding aspects of longitudinal and perpendicular digital magnetic
recording.
The work presented in this thesis is based upon numerical analysis using various simulation
methods. The environment used for implementation of simulation models is C/C + +
programming. Important results based upon bit error rate calculations have been documented
in this thesis.
This work presents the new designed Asymmetric Decoder (AD) which is modified to
take into account the jitter noise and shows that it has better performance than classical
BCJR decoders with the use of Error Correction Codes (ECC). In this work, a new method
of designing Generalised Partial Response (GPR) target and its equaliser has been discussed
and implemented which is based on maximising the ratio of the minimum squared
euclidean distance of the PR target to the noise penalty introduced by the Partial Response
(PR) filter. The results show that the new designed GPR targets have consistently
better performance in comparison to various GPR targets previously published.
Two methods of equalisation including the industry's standard PR, and a novel Soft-Feedback-
Equalisation (SFE) have been discussed which are complimentary to each other.
The work on SFE, which is a novelty of this work, was derived from the problem of Inter
Symbol Interference (ISI) and noise colouration in PR equalisation. This work also shows
that multi-level SFE with MAP/BCJR feedback based magnetic recording with ECC has
similar performance when compared to high density binary PR based magnetic recording
with ECC, thus documenting the benefits of multi-level magnetic recording. It has been
shown that 4-level PR based magnetic recording with ECC at half the density of binary PR
based magnetic recording has similar performance and higher packing density by a factor
of 2.
A novel technique of combining SFE and PR equalisation to achieve best ISI cancellation
in a iterative fashion has been discussed. A consistent gain of 0.5 dB and more
is achieved when this technique is investigated with application of Maximum Transition
Run (MTR) codes. As the length of the PR target in PR equalisation increases, the gain
achieved using this novel technique consistently increases and reaches up to 1.2 dB in case
of EEPR4 target for a bit error rate of 10-5
- …