New families of voltage-mode and current-mode filter circuits.

In some previous papers, feed forward configurations of realizing second order all pass transfer functions with complex poles by adding some configurations to a first order circuit are discussed. In this dissertation, the above idea extended to realize some other basic second order complex pole filter transfer functions. A new corollary for circuit conversion is proposed and proved. This corollary is useful for converting op amp based voltage-mode circuits to their CCII based equivalent circuits, as are other existing theorems. But the new corollary is useful for converting circuits that cannot be converted by other theorems

A 1V 8th-order 250MHz current-mode butterworth lowpass filter

Continuous-time filters can be used as preprocessing blocks in front of an analog-to-digital converter (A/D) in the receiving data path of a disk-drive read-channel system and as post processing blocks after a digital system. High-frequency continuous-time filters with low supply voltage are finding increased applications in high-speed Integrated Circuits (ICs) of telecommunication, video, and magnetic read-channel. This has been the driving force in the development of numerous continuous-time filter techniques exist today, and further ongoing research. Among the different topologies, current-mode functions exhibit higher frequency potential, simpler architectures, and lower supply voltage capabilities. Active RC filters have been used for years due to the high linearity. However, the uncertainty in cutoff frequency, mainly due to the integrated passive resistors and capacitors, limits the application. On the other hand, current conveyors, introduced in the early 1970\u27s, are now emerging as an important class of circuits. A novel current-mode active-RC filter combines the advantages of current conveyor circuits and active RC filter configuration with digital frequency tuning is proposed. With digital tuning, the fabricated central frequency is measured with respect to a provided reference frequency, and a digital code is then derived which selects the appropriate capacitor elements that will return tuning to the nominal value, within some defined tolerance (e.g., ±5%). A 1V 8th order 25OMhz current-mode Butterworth lowpass filter with digital frequency tuning has been implemented in TSMC 0.25[Mu]m CMOS technology

A Monolithic Gm-C Filter based Very Low Power, Programmable, and Multi-Channel Harmonic Discrimination System using Analog Signal Processing

A highly selective monolithic band-pass filter with programmable characteristics at micro-power operation is presented. Very low power signal processing is of great interest in wireless sensing and Internet-of-Things applications. This filter enables long-term battery powered operation of a highly selective harmonic signal discriminator for an analog signal processing system. The Gm-C biquadratic circuits were fabricated in a 0.18-μm [micrometer] CMOS process. Each 2nd-order biquad filter nominally consumes 20 μW [microwatt] and can be programmed for the desired gain (0db3dB), quality factor (5 to 20), and center-frequency from 1kHz to 100kHz. The 8th-order filter channel achieved an effective quality factor of 30 at 100kHz with an overall power consumption of 108 μW

Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies

Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters. In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process. This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms. The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time. Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB

A bipolar, semi-gaussian pulse shaping amplifier based on transconductance-C continuous time filters for use in a high resolution, small animal x-ray CT system

A new bipolar, semi-gaussian pulse shaping amplifier using transconductance-C (Gm-C) filters has been developed for use with the Oak Ridge National Laboratory (ORNL) MicroCAT small animal x-ray CT imaging system. The MicroCAT system employs Cadmium Zinc Telluride (CZT), a relatively new semiconductor detector material. The pulse shaping amplifier is based on a Gm-C filter topology and has adjustable gain, tunable filter time constants and quality factors as well as a differential signal path. The transconductor circuit design is also presented with emphasis placed upon the noise and linearity of the circuit. The architecture and experimental results for the prototype pulse shaping amplifier are also presented. The prototype was fabricated in the 1.2μ AMI NWELL CMOS process through the MOSIS program

Switched-Capacitor Programmable Sallen and Key Lowpass Filters

This thesis deals with a different approach to switched-capacitor filters than previously seen by the use of a Sallen and Key topology. It is shown that a Sallen and Key second-order topology approach to a switched-capacitor filter gives reasonable filter performance results, contrary to what the literature leads one to expect. It is also shown that the Sallen and Key second-order topology with modification to a third-order section with buffers results in a high performance switched-capacitor filter with fewer components than previous switched-capacitor filters. This results in fewer monolithic chip size requirements, reduced power requirements, and less cost. Higher order filters could be obtained by cascading either one of the second- or third-order switched-capacitor sections together. Desired filter Q values and cutoff frequencies are shown to be obtained by changing the capacitor ratios and clock frequencies, respectively