476 research outputs found

    Design and characterisation of monolithic CMOS detectors for high energy particle physics and SEU radiation tests for ATLAS Inner Tracker Upgrade readout chip

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    This thesis covers the characterisation results and the design of monolithic CMOS detectors designed in TowerJazz 180nm CMOS technology for High Energy Particle Physics applications. Three different detectors have been studied the MALTA, the Mini-MALTA and the MALTA2. The MALTA sensor showed some efficiency losses at the corners of the pixels after irradiation, which meant that it was not suitable for the radiation environments in which it was supposed to be installed. Therefore, the front-end electronics and the fabrication process were modified to overcome this issue. The Mini-MALTA prototype was designed including the above mentioned improvements, fabricated and fully characterised. Finally taking into account all the knowledge acquired during these years of developments another large scale sensor the MALTA2 has been produced which should be radiation tolerant and have very good time resolution. The description and studies of the different architectures used in this family of detectors are covered and a simulation to estimate the bandwidth capabilities have been reported. Furthermore, this work will present characterisation of single event effects in the ITkPixV1, the prototype version of the ATLAS Inner Tracker Upgrade chip for the High Luminosity LHC. Measurements were made in testbeam campaigns with high energy ions and protons to evaluate the level of single event effects in the chip

    Undergraduate and Graduate Course Descriptions, 2023 Spring

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    Wright State University undergraduate and graduate course descriptions from Spring 2023

    Optimization of Cell-Aware Test

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    Pushing the Boundaries of Spacecraft Autonomy and Resilience with a Custom Software Framework and Onboard Digital Twin

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    This research addresses the high CubeSat mission failure rates caused by inadequate software and overreliance on ground control. By applying a reliable design methodology to flight software development and developing an onboard digital twin platform with fault prediction capabilities, this study provides a solution to increase satellite resilience and autonomy, thus reducing the risk of mission failure. These findings have implications for spacecraft of all sizes, paving the way for more resilient space missions

    Low Power Memory/Memristor Devices and Systems

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    This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

    Optimization of Cell-Aware Test

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    University of Windsor Undergraduate Calendar 2023 Spring

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    https://scholar.uwindsor.ca/universitywindsorundergraduatecalendars/1023/thumbnail.jp

    AI/ML Algorithms and Applications in VLSI Design and Technology

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    An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations
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