Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

Smart HIV Testing System

The quick HIV testing method called “MiraWell Rapid HIV Test” uses a specialized testing kit to determine whether an individual’s blood is contaminated with the HIV virus or not. When a drop of blood is placed on the center of the testing kit, a simple pattern will appear in the middle of the kit to indicate the test status, i.e., positive or negative. This HIV test should be done in a small clinic or in a lab and the test must be conducted by a trained technician. A smart HIV testing system was developed through this research to eliminate the human error that is associated with the use of the quick HIV testing kits. Also, the smart HIV system will improve the testing productivity in comparison to those achieved by the trained technicians.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44004/1/10439_2005_Article_2784.pd

IDDQ Testing for CMOS VLSI

It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC’s. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X