MODELING THE PHYSICS OF FAILURE FOR ELECTRONIC PACKAGING COMPONENTS SUBJECTED TO THERMAL AND MECHANICAL LOADING

This dissertation presents three separate studies that examined electronic components using numerical modeling approaches. The use of modeling techniques provided a deeper understanding of the physical phenomena that contribute to the formation of cracks inside ceramic capacitors, damage inside plated through holes, and to dynamic fracture of MEMS structures. The modeling yielded numerical substantiations for previously proposed theoretical explanations. Multi-Layer Ceramic Capacitors (MLCCs) mounted with stiffer lead-free solder have shown greater tolerance than tin-lead solder for single cycle board bending loads with low strain rates. In contrast, flexible terminations have greater tolerance than stiffer standard terminations under the same conditions. It has been proposed that residual stresses in the capacitor account for this disparity. These stresses have been attributed to the higher solidification temperature of lead free solders coupled with the CTE mismatch between the board and the capacitor ceramic. This research indicated that the higher solidification temperatures affected the residual stresses. Inaccuracies in predicting barrel failures of plated through holes are suspected to arise from neglecting the effects of the reflow process on the copper material. This research used thermo mechanical analysis (TMA) results to model the damage in the copper above the glass transition temperature (Tg) during reflow. Damage estimates from the hysteresis plots were used to improve failure predictions. Modeling was performed to examine the theory that brittle fracture in MEMS structures is not affected by strain rates. Numerical modeling was conducted to predict the probability of dynamic failure caused by shock loads. The models used a quasi-static global gravitational load to predict the probability of brittle fracture. The research presented in this dissertation explored drivers for failure mechanisms in flex cracking of capacitors, barrel failures in plated through holes, and dynamic fracture of MEMS. The studies used numerical modeling to provide new insights into underlying physical phenomena. In each case, theoretical explanations were examined where difficult geometries and complex material properties made it difficult or impossible to obtain direct measurements

Vibration Fatigue of Leaded Solder Joint Interconnects for PCB Electronics

With the increasing prevalence of electronic equipment worldwide, there is also a decrease in the size of the components on their printed circuit boards (PCBs), leading to an increase in the density of these components. A significant amount of failure in electronic equipment is vibration fatigue of solder joints and their attachments. However, the complexity of these PCBs and their components has made finite element modeling (FEM) more complex, adding considerable time to create and analyze a model. This paper aims to provide a literature review for the vibration fatigue of leaded solder components, create a test setup, and validate an analytical solder joint stress model. The literature review provides a walkthrough on modeling PCBs and their components using FEMs and analytical models, fatigue modeling methodology, and fatigue testing data and highlights gaps in the literature. This review was important to compile due to the limited data and the rigor required to find it all when searching. With this literature review collected, testing was to be completed using an analytical model highlighted. Therefore, a setup and procedure have been developed to test the vibration fatigue of leaded solder attachments. The setup combines a test specimen, specimen mounting head, and preliminary model correlation between the test specimen and FEM. Using initial model correlations, an analytical solder joints stress model, and fatigue curves from literature, a vibration fatigue life prediction was made for the test specimen, and tests were run. However, the results were inconclusive and further testing is deemed necessary. Suggestions have been made, such as picking other analytical models to test, modifying the test setup, and increasing the fidelity of local areas in the FEM

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Development and reliability of a direct access sensor using flip chip on flex technology with anisotropic conductive adhesive

Technological developments in biomedical microsystems are opening up new opportunities to improve healthcare procedures. Swallowable diagnostic sensing capsules are an example of these. In none of the diagnostic sensing capsules, is the sensor’s first level packaging achieved via Flip Chip Over Hole (FCOH) method using Anisotropic Conductive Adhesive (ACA). In a capsule application with direct access sensor (DAS), ACA not only provides the electrical interconnection but simultaneously seals the interconnect area and the underlying electronics. The development showed that the ACA FCOH was a viable option for the DAS interconnection. Adequate adhesive formed a strong joint that withstood a shear stress of 120N/mm2 and a compressive stress of 6N required to secure the final sensor assembly in place before encapsulation. Electrical characterization of the ACA joint in a fluid environment showed that the ACA was saturated with moisture and that the ions in the solution actively contributed to the leakage current, characterized by the varying rate of change of conductance. Long term hygrothermal aging of the ACA joint showed that a thermal strain of 0.004 and a hygroscopic strain of 0.0052 were present and resulted in a fatigue like process. In-vitro tests showed that high temperature and acidity had a deleterious effect of the ACA and its joint. It also showed that the ACA contact joints positioned at around or over 1mm would survive the gastrointestinal (GI) fluids and would be able to provide a reliable contact during the entire 72hr of the GI transit time. A final capsule demonstrator was achieved by successfully integrating the DAS, the battery and the final foldable circuitry into a glycerine capsule. Final capsule soak tests suggested that the silicone encapsulated system could survive the 72hr gut transition

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame

Compliant Chip-to-Package Interconnects for Wafer Level Packaging

Ph.DDOCTOR OF PHILOSOPH

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for ‘power-by-the-hour’ commercial aircraft operation business models. [Continues.